Atomic operation in remote storage and device for executing this operation

1. A process for controlling an atomic operation in a first register (OPA) by a data processing system (1, 2), said first register being disposed at a location remote from said data processing system, characterized in that said process comprises two steps followed by a third step which is a function of the result of the first two steps, the first step comprising loading in a second register (81, 82), locally attached to said first register (OPA), a value known by said data processing system (1,2); the second step comprising comparing, locally relative to said first register (OPA), the value of the content of the second register (81, 82) to a current value in said first register (OPA) and when said value of the content of the second register (81, 82) is equal to the current value in said first register (OPA), replacing said current value with a new value, communicated by the data processing system (1, 2); and the third step comprising communicating to the data processing system (1, 2) said current value of said first register; the second register (81, 82) is located in a controller (7, 16, 17) locally attached to a memory unit (8) disposed at a location remote from said data processing system (1, 2); and said controller (7, 16, 17) comprises a third register (77, 78) having an input operatively connected for receiving data originating from the memory unit (8) and further including the step of writing the current value of the first register (OPA) into said controller following a command to partially write a block of the memory unit (8) containing said first register (OPA) so as to write the new value into said first register (OPA).

2. A process for controlling an atomic operation in a first register (OPA) by a data processing system (1, 2), an expanded storage (3) disposed at a location physically remote from said data processing system, said expanded storage (3) including the first register (OPA) and a second register (81, 82) connected to a memory unit (8) disposed at the location of said expanded storage (3), said expanded storage (3) further including said controller (7, 16, 17) having a third register (77, 78) with an input operatively connected for receiving data originating from the memory unit (8) wherein said process comprises two steps followed by a third step which is a function of the result of the first two steps, the first step comprising loading in a second register (81, 82), locally attached to said first register (OPA), a value known by said data processing system (1,2); the second step comprising comparing locally in said expanded storage (3), the value of the content of the second register (81, 82) to a current value in said first register (OPA) and when said value of the content of the second register (81, 82) is equal to the current value in said first register (OPA), replacing said current value with a new value, communicated by the data processing system (1, 2); and the third step comprising communicating to the data processing system (1, 2) from the expanded storage (3) said current value of said first register; and further including the step of writing the current value of the first register (OPA) into said controller following a command to partially write a block of the memory unit (8) containing said first register (OPA) so as to write the new value into said first register (OPA).

3. The process for controlling an atomic operation according to claim 2, characterized in that the current value is replaced by the new value if and only if the result of the comparison indicates that the content of the second register is equal to the current value.

4. The process for controlling the atomic operation according to claim 3, further comprising repeating the first step in the event of any interference occurring before the execution of the second step, and executing the third step upon any interference occurring during the execution of the second step.

5. The process for controlling an atomic operation according to claim 2, characterized in that the current value is replaced by the new value if and only if the result of the comparison indicates that the content of the second register is equal to the current value.

6. The process for controlling the atomic operation according to claim 5, further comprising repeating the first step in the event of any interference occurring before the execution of the second step, and executing the third step upon any interference occurring during the execution of the second step.

7. The process for controlling atomic operation according to claim 2, characterized in that the current value is replaced by the new value no matter what the result of the comparison and in that the first two steps are always followed by the third step.

8. The process for controlling atomic operation according to claim 1, characterized in that the current value is replaced by the new value no matter what the result of the comparison and in that the first two steps are always followed by the third step.

9. A control device comprising a memory stack (64), a first multiplexer (67) connected to said stack, and a first combinational logic circuit (62), said stack receiving at least a first and a second input, said first input being connected to a first bus (M2CB) via said multiplexer, a memory unit (8) connected to said first bus (M2CB) for transferring data originating from said memory unit to said stack via said multiplexer, a second bus (L2CB) for transferring data originating from a remote data processing system (1, 2) to said second input of said stack (64), a third bus (C2MB), said first combinational logic circuit (62) having an output connected to said third bus (C2MB) and an input connected to an output of said memory stack (64), a first register (77, 78) having an input operatively connected to the first bus (M2CB) for receiving data originating from the memory unit (8) and an output for sending data to the remote data processing system (1, 2), a second multiplexer (68) having an input connected to receive the output of said first register (77, 78) and an output connected to a fourth bus (C2LB), and a second combinational logic circuit (72) for disabling the writing of at least one input of the stack (64) and for sending data directed to said disabled input to said first register (77, 78).

10. The device according to claim 9, characterized in that it further comprises: a second register (81, 82) having an input connected to the second bus (L2CB); and a comparator (79) having a first input connected to an output of the first register (77, 78), a second input connected to an output of the second register (81, 82) and an output operatively connected for driving at least one output of the memory stack (64).

11. The control device according to claim 10, further comprising a locking device (74) adapted to adhere to a circular-type priority for access to the memory unit (8) by a plurality of controllers (7, 16, 17).

12. The device according to claim 11, characterized in that said device is duplicated n times so as to allow processing of n indivisible operations simultaneously, a critical section being limited to a local partial write time.

13. The control device according to claim 9, further comprising a locking device (74) adapted to adhere to a circular-type priority for access to the memory unit (8) by a plurality of storage controllers (7, 16, 17).

14. The device according to claim 13, characterized in that said device is duplicated n times so as to allow processing of n indivisible operations simultaneously, a critical section being limited to a local partial write time.