Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a substrate; a line formed on said substrate; and a crystalline semiconductor film containing silicon in contact with said line, wherein: said line electrically connects said crystalline semiconductor film to a location outside of said semiconductor device, and said line contains an element which functions as a catalyst for crystallizing said crystalline semiconductor film on annealing.
2. A semiconductor device according to claim 1, further comprising an insulating film formed on said line, wherein said crystalline semiconductor film is in contact with said line through a contact hole formed in said insulating film.
3. A semiconductor device according to claim 1, wherein said line is formed of a single layer film or of a multi-layer film made of a constituting material containing at least one material selected from the group consisting of nickel, iron, cobalt and platinum.
4. A thin film transistor, comprising: a substrate; a line formed on said substrate; a crystalline semiconductor film containing silicon in contact with said line; a gate insulating film formed on said crystalline semiconductor film; and a gate electrode formed on said gate insulating film, wherein said line electrically connects said crystalline semiconductor film to a location outside of said semiconductor device, and said line contains an element which functions as a catalyst for crystallizing said crystalline semiconductor film on annealing.
5. A thin film transistor according to claim 4, further comprising an insulating film formed on said line, wherein said crystalline semiconductor film is in contact with said line through a contact hole formed in said insulating film.
6. A thin film transistor according to claim 4, wherein: said crystalline semiconductor film includes a source region and a drain region; and said source region and said drain region are selectively doped with a group III element or a group V element as an impurity.
7. A thin film transistor according to claim 6, wherein said impurity is doped self-aligningly with said gate electrode being used as a mask.
8. A thin film transistor according to claim 4, further comprising a shielding film formed on said substrate in the same step as for said line.
9. A thin film transistor according to claim 4, wherein said line is formed of a single layer film or of a multi-layer film made of a constituting material containing at least one material selected from the group consisting of nickel, iron, cobalt and platinum.
10. A liquid crystal display apparatus, comprising at least one thin film transistor according to claim 4.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
Unknown
October 10, 2000
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