HDP-CVD method for spacer formation

1. A method for forming a gate structure of a semiconductor device, said method comprising the steps of: forming a gate oxide layer on a wafer; forming a polysilicon layer on said gate oxide layer; patterning said polysilicon layer to fabricate a gate stack; depositing an first layer on said wafer, wherein a building of sharp ridges occurs over said gate stack; conformally depositing a second layer; and anisotropically etching said second layer to form spacers against sidewall of said gate stack, wherein at least portions of said second layer remains on said sharp ridges.

2. The method according to claim 1, further comprising a method of forming a contact based on said gate structure comprising the steps of: depositing a third layer on said wafer; and anisotropically etching said third layer to form a contact on said wafer.

3. The method according to claim 2, wherein portions of said first layer that placed between two of said gate stacks and non-covered by said second layer is etched when said third layer being anisotropically etched.

4. The method according to claim 2, wherein said second layer and said third layer have selectivity when performing said anisotropically etching.

5. The method according to claim 1, wherein said first layer is formed by an HDP-CVD (High-Density Plasma-Chemical Vapor Deposition) process.

6. The method according to claim 5, wherein said first layer is grown under a circumstance with a temperature from -10 to 100.degree. C., an O.sub.2 gas flow into a chamber from 3 to 300 sccm, a SiH.sub.4 gas flow into said chamber from 3 to 300 sccm, and a pressure in said chamber from 10 to 100 milliTorr for depositing about 0.1 to 3 minutes.

7. The method according to claim 1, wherein said spacers are thicker than said portions of said second layer that remained on said sharp ridges of said gate stack.

8. The method according to claim 1, wherein said polysilicon layer comprising a metal layer on said polysilicon layer.

9. A method for forming a gate structure of a semiconductor device, said method comprising the steps of: forming a gate oxide layer on a wafer; forming a polysilicon layer on said gate oxide layer; patterning said polysilicon layer to fabricate a gate stack; depositing an HDP-CVD (High-Density Plasma-Chemical Vapor Deposition) deposition layer on said wafer, wherein said HDP-CVD deposition layer forms a building of sharp ridges over said gate stack; conformally depositing a cap deposition layer; and anisotropically etching said cap deposition layer to form spacers against sidewall of said gate stack, wherein at least portions of said cap deposition layer remains on said sharp ridges.

10. The method according to claim 9, further comprising a method of forming a contact based on said gate structure comprising the steps of: depositing an internal dielectric deposition layer on said wafer; and anisotropically etching said internal dielectric deposition layer to form a contact on said wafer placed between two of said gate stacks.

11. The method according to claim 10, wherein portions of said HDP-CVD deposition layer that placed between two of said gate stacks and non-covered by said cap deposition layer are etched when said internal dielectric deposition layer being anisotropically etched.

12. The method according to claim 10, wherein said cap deposition layer and said internal dielectric deposition layer have selectivity when performing said anisotropically etching.

13. The method according to claim 9, wherein said HDP-CVD deposition layer is grown under a circumstance with a temperature from -10 to 100.degree. C., an O.sub.2 and SiH.sub.4 gas flow into a chamber from 3 to 300 sccm, a SiH.sub.4 gas flow into said chamber from 3 to 300 sccm, and a pressure in said chamber from 10 to 100 milliTorr for depositing about 0.1 to 3 minutes.

14. The method according to claim 9, wherein said spacers are thicker than said portions of said cap deposition layer that remained on said sharp ridges of said gate stack.

15. The method according to claim 9, wherein said polysilicon layer comprises a metal layer on said polysilicon layer.

16. A method of forming a self-aligned contact structure for a semiconductor device, said method comprising the steps of: forming a gate oxide layer on a wafer; forming a polysilicon layer on said gate oxide layer; forming a metal layer on said polysilicon layer; patterning said polysilicon layer and said metal layer to fabricate a gate stack; depositing an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) deposition layer on said wafer, wherein said HDP-CVD deposition layer forms a building of sharp ridges over said gate stack; conformally depositing a cap deposition layer; anisotropically etching said cap deposition layer to form spacers against sidewall of said gate stack, wherein at least portions of said cap deposition layer remains on said sharp ridges; depositing an internal dielectric deposition layer on said wafer; and anisotropically etching said internal dielectric deposition layer to form a contact on said wafer.

17. The method according to claim 16, wherein portions of said HDP-CVD deposition layer that placed between two of said gate stacks and non-covered by said second layer is etched when said internal dielectric deposition layer being anisotropically etched.

18. The method according to claim 16, wherein said cap deposition layer and said internal dielectric deposition layer have selectivity when performing said anisotropically etching.

19. The method according to claim 16, wherein said HDP-CVD deposition layer is grown under a circumstance with a temperature from -10 to 100.degree. C., an O.sub.2 and SiH.sub.4 gas flow into a chamber from 3 to 300 sccm, a SiH.sub.4 gas flow into said chamber from 3 to 300 sccm, and a pressure in said chamber from 10 to 100 milliTorr for depositing about 0.1 to 3 minutes.

20. The method according to claim 16, wherein said spacers are thicker than said portions of said cap deposition layer that remained on said sharp ridges of said gate stack.