Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics

1. A semiconductor device comprising: a substrate; a dielectric layer on the substrate; a first patterned metal layer on the dielectric layer; a gap fill dielectric layer on the first patterned metal layer; a dielectric cap layer on the gap fill dielectric layer; a second patterned metal layer on the dielectric cap layer; a conductive via between a metal feature of the first patterned metal layer and a metal feature of the second patterned metal layer; and a substantially conformal silicon oxynitride (SiON) layer on the second patterned metal layer, wherein the dielectric cap layer has a thickness of at least about 1000 Angstroms (.ANG.) to prevent any substantial deformation and/or delamination of the substantially conformal SiON layer due to outgassing of the gap fill dielectric layer upon heating of the gap fill dielectric layer to a temperature of at least about 300.degree. C.

2. The semiconductor device as recited in claim 1, wherein the dielectric cap layer has a thickness of at least about 2000 .ANG..

3. The semiconductor device as recited in claim 1, wherein the dielectric cap layer comprises a silicone oxide derived from silane or tetraethyl orthosilicate.

4. The semiconductor device as recited in claim 1, further comprising a substantially conformal SiON layer on both the first patterned metal layer and the dielectric layer.

5. The semiconductor device as recited in claim 1, wherein the gap fill dielectric layer comprises a material selected from the group consisting of spin-on-glass and hydrogen silsesquioxane.

6. The semiconductor device as recited in claim 1, wherein the conformal SiON layer has a thickness of about 500 .ANG. to about 3000 .ANG..