Multiple level cache memory with overlapped L1 and L2 memory access

1. A method of providing data from a cache to a processor of a computer system, comprising the steps of: loading a value into a lower level of the cache; issuing a request from the processor that the value be supplied by a higher level of the cache; in response to said issuing step, determining that a cache miss of the value has occurred at the higher level of the cache; forwarding the request to the lower level of the cache during said determining step, including the step of decoding an address related to a particular location of the value in a system memory device of the computer system; and in response to said determining step, supplying the value from the lower level of the cache.

2. The method of claim 1 wherein the value is supplied from the lower level of the cache directly to the processor.

3. The method of claim 1 wherein said decoding step includes the step of operating a plurality of decoders in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests.

4. The method of claim 1 wherein said supplying step includes the step of gating the address to a plurality of memory array word line drivers of the lower level of the cache.

5. The method of claim 1 wherein said decoding step includes the step of immediately decoding a plurality of bits of the address that do not require virtual-to-real translation.

6. The method of claim 5 wherein said decoding step includes the step of translating another plurality of bits of the address prior to completion of said determining step.

7. A cache for providing values to a processor of a computer system, the cache comprising: a higher cache level; a lower cache level; and means for reducing memory access latency when a cache miss of a value has occurred at said higher cache level and the value is supplied from said lower cache level, said reducing means providing an overlap of a first access of said higher cache level and a second access of said lower cache level, by forwarding a request of the value from the processor to said lower cache level while said first cache level determines whether a cache miss has occurred, the request being forwarded by decoding an address related to a particular location of the value in a system memory device of the computer system.

8. The cache of claim 7 wherein: said higher cache level is a first cache level connected to the processor; and said lower cache level is a second cache level connected to said first cache level.

9. The cache of claim 7 wherein said second cache level is further connected to a third cache level.

10. The cache of claim 7 wherein said means for reducing said memory access latency supplies the value from said lower cache level directly to the processor.

11. The cache of claim 8 wherein reducing means supplies the value by gating the address to a plurality of memory array word line drivers of said lower cache level.