System with DLL

1. An integrated circuit which provides an output clock signal synchronized to an internal clock signal which operates the integrated circuit, comprising: a clock generator circuit having an input for receiving the internal clock signal, and first and second outputs for respectively providing first and second clock signals having first and second frequencies, respectively, said first frequency being an integer multiple greater than or equal to one of said second frequency, wherein said clock generator circuit comprises an analog phase locked loop; a clock shifting circuit having first and second inputs respectively coupled to said first and second outputs of said clock generator circuit, a first output for providing a shifted clock signal, and a second output for providing a reference clock signal, wherein said clock shifting circuit divides said first input by a predetermined divide ratio to provide a divided clock signal and selectively delays said divided clock signal by a selected delay time to provide said shifted clock signal, and provides said reference clock signal by dividing said second input by a divide ratio; wherein said clock shifting circuit comprises: a register for storing a control bit and providing an output thereof responsive to a logic state of said control bit; and a multiplexer having true and complement input terminals each receiving said first clock signal, a control input terminal coupled to said output of said register, and an output terminal for providing said shifted clock signal; and a delay locked loop having a reference clock input for receiving said second clock signal, a feedback clock input for receiving a feedback clock signal, a clock input for receiving the shifted clock signal, and a clock output for providing the output clock signal, wherein the delay locked loop delays the shifted clock signal by a variable delay time proportional to a phase difference between the reference clock signal and the feedback clock signal.

2. An integrated circuit which provides an output clock signal synchronized to an internal clock signal which operates the integrated circuit, comprising: a clock generator circuit having an input for receiving the internal clock signal, and first and second outputs for respectively providing first and second clock signals having first and second frequencies, respectively, said first frequency being an integer multiple greater than or equal to one of said second frequency, wherein said clock generator circuit comprises an analog phase locked loop; a clock shifting circuit having first and second inputs respectively coupled to said first and second outputs of said clock generator circuit, a first output for providing a shifted clock signal, and a second output for providing a reference clock signal, wherein said clock shifting circuit divides said first input by a predetermined divide ratio to provide a divided clock signal and selectively delays said divided clock signal by a selected delay time to provide said shifted clock signal, and provides said reference clock signal by dividing said second input by a divide ratio; wherein said clock shifting circuit comprises: a clock divider having a clock input for receiving said first clock signal, a divide input for receiving said divide ratio, a reset input, and an output for providing said shifted clock signal; and a clock control logic circuit having a clock input for receiving said second clock signal, a divide input for receiving an interface ratio, a delay input coupled to said delay locked loop for receiving a digital value representative of said variable delay time, a first output coupled to said divide input of said clock divider for providing said divide ratio, and a reset output coupled to said reset input of said clock divider for providing a reset signal; and a delay locked loop having a reference clock input for receiving said second clock signal, a feedback clock input for receiving a feedback clock signal, a clock input for receiving the shifted clock signal, and a clock output for providing the output clock signal, wherein the delay locked loop delays the shifted clock signal by a variable delay time proportional to a phase difference between the reference clock signal and the feedback clock signal.

3. The integrated circuit of claim 2 wherein said clock control logic circuit provides said divide ratio in response to both said interface ratio and to a frequency ratio of said first clock signal to said second clock signal.

4. The integrated circuit of claim 2 wherein said clock control logic circuit deactivates said reset signal at a time relative to a start of a cycle of said reference clock signal equal to an integer number of half periods of said second clock signal.

5. The integrated circuit of claim 4 wherein said clock control logic circuit iteratively changes said integer number of half periods of said second clock signal until said delay locked loop locks.

6. The integrated circuit of claim 5 wherein said clock control logic circuit determines said integer number of half periods of said second clock signal such that said selected delay time is between minimum and maximum delay times of said delay locked loop.

7. The integrated circuit of claim 5 wherein said clock control logic circuit further provides a lock cycle complete output signal when either said delay locked loop has locked, or said clock control logic circuit has iteratively changed said integer number of half periods of said second clock signal for a predetermined number of times without said delay locked loop locking.