Memory circuit for changing boost ratio

1. A memory circuit, which includes non-volatile memory, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and non-volatile memory disposed at the intersections thereof; a row decoder circuit for driving a word line at a boosted voltage level during reading; and a booster circuit for boosting a power source voltage with a predetermined ratio during reading to generate said boosted voltage; wherein said booster circuit varies said predetermined ratio according to the level of said power source voltage to maintain the boosted voltage within a prescribed range regardless of the change of the power source voltage.

2. A memory circuit, which includes non-volatile memory, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and non-volatile memory disposed at the intersections thereof; a row decoder circuit for driving said word lines at a boosted voltage level during reading; and a booster circuit for boosting a power source voltage to a predetermined ratio and generating said boosted voltage; wherein said booster circuit varies said predetermined ratio according to the level of said power source voltage and said booster circuit detects the level of said power source voltage in response to an address transition detection signal detecting transitions of supplied address, and changes said predetermined ratio according to the detected level.

3. A memory circuit, which includes non-volatile memory, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and non-volatile memory cell transistors disposed at the intersections thereof; a row decoder circuit for driving a word line at a boosted voltage level during reading; a reference memory cell transistor having said non-volatile memory cell transistor whose gate is driven at said boosted voltage; a sense amp for detecting data of said memory cell transistors, corresponding to the currents of said reference memory cell transistor and the memory cell transistors within said memory cell array, during reading; and a booster circuit for boosting a power source voltage with a predetermined ratio during reading to generate said boosted voltage; wherein said booster circuit varies said predetermined ratio according to the level of said power source voltage to maintain the boosted voltage within a prescribed range regardless of the change of the power source voltage.

4. A memory circuit, which includes non-volatile memory, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and non-volatile memory cell transistors disposed at the intersections thereof; a row decoder circuit for driving said word lines at a boosted voltage level during reading; a reference memory cell transistor having said non-volatile memory cell transistor whose gate is driven at said boosted voltage; a sense amp for detecting data of said memory cell transistors, corresponding to the currents of said reference memory cell transistor and the memory cell transistors within said memory cell array, during reading; and a booster circuit for boosting a power source voltage to a predetermined ratio and generating said boosted voltage; wherein said booster circuit varies said predetermined ratio according to the level of said power source voltage and said predetermined ratio is varied so that said boosted voltage level is controlled to a level so that the conductive current of said reference memory cell transistor is greater than the leakage current of said memory cell transistor.

5. The memory circuit according to claim 4, wherein: said predetermined ratio is varied to become a first boost ratio when said power source voltage is a first voltage, and to become a second boost ratio, higher than said first boost ratio, when said power source voltage is a second voltage which is lower than said first voltage.

6. The memory circuit according to claim 4, further comprising a leakage current reference transistor including said non-volatile memory cell transistor and generating the allowable leakage current; wherein: said predetermined ratio is varied to be further higher when the conductive current of said reference memory cell transistor becomes less than the conductive current of said leakage current reference transistor.

7. A memory circuit, which includes non-volatile memory, comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and non-volatile memory cell transistors disposed at the intersections thereof; a row decoder circuit for driving said word lines at a boosted voltage level during reading; a reference memory cell transistor having said non-volatile memory cell transistor whose gate is driven at said boosted voltage; a sense amp for detecting data of said memory cell transistors, corresponding to the currents of said reference memory cell transistor and the memory cell transistors within said memory cell array, during reading; and a booster circuit for boosting a power source voltage to a predetermined ratio and generating said boosted voltage; wherein said booster circuit varies said predetermined ratio according to the level of said power source voltage and said predetermined ratio is limited so that a prescribed write operation is not carried out for selected non-volatile memory cell transistor connected to the word lines when said word lines are driven at said boosted voltage.