Semiconductor storage device

1. A semiconductor storage device comprising: a memory cell array in which a plurality of memory cells are arranged at points of intersection which are formed between a plurality of column lines and a plurality of row lines; a row redundancy cell array in which a plurality of redundancy cells are arranged in connection with a plurality of redundancy row lines, and the redundancy cells are used as replacements for the memory cells containing a defective memory cell in the memory cell array with respect to each address; a row line selector for selecting a row line of the memory cell array in response to an address input thereto; a column line selector for selecting a column line of the memory cell array in response to the address input thereto; a defective row line address storage for storing a defective row line address representative of a row line being connected with the defective memory cell; and a redundancy row line selector for selecting a redundancy row line of the row redundancy cell array in response to the defective row line address and for producing an inhibit signal to inhibit the row line selector from selecting the row line, wherein in response to a control signal given from an external, the redundancy row line selector stops outputting the inhibit signal but selects all of the redundancy row lines of the row redundancy cell array collectively.

2. A semiconductor storage device according to claim 1 wherein if the control signal designates a test mode, the redundancy row line selector stops outputting the inhibit signal but selects all of the redundancy row lines of the row redundancy cell area collectively.

3. A semiconductor storage device according to claim 1 wherein the redundancy row line selector stops outputting the inhibit signal but selects all of the redundancy row lines of the row redundancy cell area collectively, regardless of the address input thereto if the control signal designates a burn-in test mode, the redundancy row line selector selects a redundancy row line designated by the address input thereto if the control signal designates a test mode for the row redundancy cell array, or the redundancy row line selector selects the redundancy row line based on the defective row line address and outputs the inhibit signal for inhibiting the row line selector from operating if the control signal designates a normal operation mode.

4. A semiconductor storage device according to any one of claim 1 wherein the redundancy row line selector selects all of the redundancy row lines in response to results of logical operations being effected on the control signal and readouts of the row redundancy cells if the control signal designates a burn-in test mode.

5. A semiconductor storage device according to any one of claim 1 wherein the redundancy row line selector produces a new inhibit signal in response to a result of a logical operation being effected on the control signal and the inhibit signal, and wherein the redundancy row line selector stops outputting the new inhibit signal if the control signal designates a burn-in test mode.

6. A semiconductor storage device according to any one of claim 1 wherein the redundancy row line selector selects all of the redundancy row lines in response to results of logical operations being effected on the control signal and readouts of the row redundancy cells if the control signal designates a burn-in test mode, and wherein the redundancy row line selector produces a new inhibit signal in response to a result of a logical operation being effected on the control signal and the inhibit signal, and wherein the redundancy row line selector stops outputting the new inhibit signal if the control signal designates the burn-in test mode.

7. A semiconductor storage device comprising: a row line selector for sequentially selecting a plurality of row lines; a redundancy row line selector for sequentially selecting a plurality of redundancy row lines; and a row line selection invalidator for outputting a signal invalidating the row line selector if the redundancy row line selector selects the redundancy row line in a first mode, wherein a second mode allows the row line selector to select the row lines while simultaneously allowing the redundancy row line selector to select the redundancy row lines.

8. A semiconductor storage device according to claim 7 further comprising: a row redundancy test decoder; and a row redundancy address setting circuit, wherein a redundancy row line is to be selected based on either an output of the row redundancy test decoder or an output of the row redundancy address setting circuit, and wherein the signal invalidating the row line selector is output based on the output of the row redundancy test decoder.

9. A semiconductor storage device comprising: a row line selector for sequentially selecting a plurality of row lines; a redundancy row line selector for sequentially selecting a plurality of redundancy row lines; a row line selection invalidator for outputting a signal invalidating the row line selector if the redundancy row line selector selects the redundancy row line in a first mode; and an inhibitor for inhibiting the row line selection invalidator from outputting the signal invalidating the row line selector if the redundancy row line selector selects the redundancy row line in a second mode.

10. A semiconductor storage device comprising: a row redundancy cell array in which a plurality of row redundancy cells are arranged in connection with a plurality of redundancy word lines respectively; a memory cell array in which a plurality of memory cells are arranged in connection with word lines respectively; a mode designator for designating at least a burn-in test mode; a redundancy word line selector for selecting the plurality of redundancy word lines collectively, so that stress is applied to the plurality of redundancy cells collectively in response to the burn-in test mode; and a word line selector for selecting the plurality of word lines collectively, so that stress is applied to the plurality of memory cells collectively in response to the burn-in test mode, wherein stress is applied simultaneously to the plurality of redundancy word lines and the plurality of word lines collectively, so that a burn-in test is performed on the plurality of redundancy cells and the plurality of memory cells collectively in the burn-in test mode.

11. A semiconductor storage device according to claim 10 wherein the redundancy word line selector further comprises a row redundancy address storage for storing a defective word line address designating a word line being connected with a defective memory cell within the memory cell array in advance; a row redundancy tester for selecting the redundancy word lines respectively in response to an input address under control of the mode designator; and a word line selection inhibitor for inhibiting the word line selector from selecting the word lines of the memory cell array.

12. A semiconductor storage device according to claim 11 wherein when the mode designator designates a normal operation mode, the word line selector sequentially selects the word lines in response to the input address, and wherein if the input address coincides with the defective word line address, the word line selection inhibitor inhibits the word line selector from selecting the word line designated by the defective word line address while the redundancy word line selector selects a redundancy word line as a replacement of the word line in response to the defective word line address.

13. A semiconductor storage device according to claim 11 wherein when the mode designator designates a defectiveness test mode, the row redundancy tester sequentially selects the redundancy word lines in response to the input address.

14. A semiconductor storage device according to claim 10 further comprising: a bit line selector for sequentially selecting a plurality of bit lines, so that stored information is read out from a memory cell or a redundancy cell, which is located at a point of intersection between a selected bit line and a selected word line or a selected redundancy line.

15. A burn-in test method for a semiconductor storage device containing a row redundancy cell array in which a plurality of redundancy cells are arranged in connection with a plurality of redundancy word lines respectively and a memory cell array in which a plurality of memory cells are arranged in connection with a plurality of word lines respectively, said burn-in test method comprising the steps of: designating a burn-in test mode; collectively activating the plurality of redundancy word lines in response to the burn-in test mode; collectively activating the plurality of word lines in response to the burn-in test mode; and applying stress simultaneously to the plurality of redundancy word lines being activated and the plurality of word lines being activated, so that a burn-in test is performed on the plurality of redundancy cells and the plurality of memory cells collectively.

16. A word line activation control method for a semiconductor storage device containing a row redundancy cell array in which a plurality of redundancy cells are arranged in connection with a plurality of redundancy word lines respectively and a memory cell array in which a plurality of memory cells are arranged in connection with a plurality of word lines respectively, said word line activation control method comprising the steps of: detecting coincidence between an input address and a defective word line address designating a word line being connected with a defective memory cell within the memory cell array; inhibiting the word line from being activated; and activating a redundancy word line of the row redundancy cell array as a replacement of the word line.

17. A defectiveness test method for a semiconductor storage device containing a row redundancy cell array in which a plurality of redundancy cells are arranged in connection with a plurality of redundancy word lines respectively and a memory cell array in which a plurality of memory cells are arranged in connection with a plurality of word lines respectively, said defectiveness test method comprising the steps of: sequentially activating the plurality of redundancy word lines; and applying stress sequentially to the plurality of redundancy word lines, so that defectiveness is checked with respect to each of the redundancy cells connected with the redundancy word line being activated.

18. A semiconductor storage device according to claim 2 wherein the redundancy row line selector stops outputting the inhibit signal but selects all of the redundancy row lines of the row redundancy cell area collectively, regardless of the address input thereto if the control signal designates a bum-in test mode, the redundancy row line selector selects a redundancy row line designated by the address input thereto if the control signal designates a test mode for the row redundancy cell array, or the redundancy row line selector selects the redundancy row line based on the defective row line address and outputs the inhibit signal for inhibiting the row line selector from operating if the control signal designates a normal operation mode.

19. A semiconductor storage device according to claim 12 wherein when the mode designator designates a defectiveness test mode, the row redundancy tester sequentially selects the redundancy word lines in response to the input address.