Method of forming shallow trench isolation by HDPCVD oxide

1. A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride layer and pad oxide layer into said semiconductor substrate wherein there is at least one first region having a wide nitride area between two of said isolation trenches and at least one second region having a narrow nitride area between another two of said isolation trenches; depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide layer has a first thickness in said first region over said wide nitride area and a second thickness in said second region over said narrow nitride area wherein said first thickness is larger than said second thickness; forming a photoresist mask over said high density plasma oxide layer and exposing said substrate to actinic light wherein a central portion of said first region is exposed; etching away said high density plasma oxide layer within said central portion of said first region wherein said central portion is about 80% of the width of said first region thereby leaving only said second thickness of said high density plasma oxide layer to be planarized; polishing away said high density plasma oxide layer remaining wherein said substrate is planarized; and completing the fabrication of said integrated circuit device.

2. The method according to claim 1 further comprising growing a lining oxide layer on the bottom and sidewall surfaces of said isolation trenches before said step of depositing of said high density plasma oxide layer.

3. The method according to claim 1 wherein said high density plasma oxide layer is deposited to a thickness of about 7000 Angstroms.

4. The method according to claim 1 wherein said step of etching away said high density plasma oxide layer within said central portion of said first region allows for said step of polishing to be uniform.

5. The method according to claim 1 wherein said step of polishing is done by chemical mechanical polishing.

6. The method according to claim 1 wherein said step of completing fabrication of said integrated circuit device comprises: etching away said silicon nitride layer; removing said pad oxide layer; and fabricating semiconductor device structures in and on said semiconductor substrate between said isolation trenches.

7. A method of manufacturing an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride layer and pad oxide layer into said semiconductor substrate wherein there is at least one first region having a wide nitride area between two of said isolation trenches and at least one second region having a narrow nitride area between another two of said isolation trenches; depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide layer has a first thickness in said first region over said wide nitride area and a second thickness in said second region over said narrow nitride area wherein said first thickness is larger than said second thickness; forming a photoresist mask over said high density plasma oxide layer and exposing said substrate to actinic light wherein a central portion of said first region is exposed; etching away said high density plasma oxide layer within said central portion of said first region wherein said central portion is about 80% of the width of said first region; polishing away said high density plasma oxide layer remaining wherein said substrate is planarized; thereafter etching away said silicon nitride layer and removing said pad oxide layer; fabricating semiconductor device structures in and on said semiconductor substrate between said isolation trenches; and completing the fabrication of said integrated circuit device.

8. The method according to claim 7 further comprising growing a lining oxide layer on the bottom and sidewall surfaces of said isolation trenches before said step of depositing of said high density plasma oxide layer.

9. The method according to claim 7 wherein said high density plasma oxide layer is deposited to a thickness of about 7000 Angstroms.

10. The method according to claim 7 wherein said step of etching away said high density plasma oxide layer within said central portion of said first region allows for said step of polishing to be uniform.

11. The method according to claim 7 wherein said step of polishing is done by chemical mechanical polishing.

12. The method according to claim 7 wherein said semiconductor device structures comprise gate electrodes and source and drain regions and electrical connections between said device structures.

13. A method of forming shallow trench isolation in the fabrication of an integrated circuit device comprising: providing a pad oxide layer over the surface of a semiconductor substrate; depositing a nitride layer overlying said pad oxide layer; etching a plurality of isolation trenches through said nitride layer and pad oxide layer into said semiconductor substrate wherein there is at least one first region having a wide nitride area between two of said isolation trenches and at least one second region having a narrow nitride area between another two of said isolation trenches; depositing a high density plasma oxide layer over said nitride layer and within said isolation trenches wherein said high density plasma oxide layer fills said isolation trenches and wherein said high density plasma oxide layer has a first thickness in said first region over said wide nitride area and a second thickness in said second region over said narrow nitride area wherein said first thickness is larger than said second thickness; forming a photoresist mask over said high density plasma oxide layer and exposing said substrate to actinic light wherein a central portion of said first region is exposed; etching away said high density plasma oxide layer within said central portion of said first region wherein said central portion is about 80% of the width of said first region; polishing away said high density plasma oxide layer remaining wherein said substrate is planarized; etching away said silicon nitride layer; and removing said pad oxide layer to complete the formation of said shallow trench isolation in the fabrication of said integrated circuit device.

14. The method according to claim 13 further comprising growing a lining oxide layer on the bottom and sidewall surfaces of said isolation trenches before said step of depositing of said high density plasma oxide layer.

15. The method according to claim 13 wherein said high density plasma oxide layer is deposited to a thickness of about 7000 Angstroms.

16. The method according to claim 13 wherein said step of etching away said high density plasma oxide layer within said central portion of said first region allows for said step of polishing to be uniform.

17. The method according to claim 13 wherein said step of polishing is done by chemical mechanical polishing.