Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first dielectric layer overlying the chip and containing a hole, the hole overlying one of the contact pads; a conductive trace extending from a location inside the hole along a surface of the first dielectric layer, the conductive trace being in electrical contact with the pad; a second dielectric layer overlying the first dielectric layer and conductive trace and containing a second hole, the second hole overlying the trace; a first conductive bump formed in the second hole and extending above the second dielectric layer; an encapsulant layer overlying the second dielectric layer, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
2. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is located directly over a side edge of the semiconductor chip.
3. The semiconductor chip package of claim 1 wherein a side edge of the first and second dielectric layers and the encapsulant layer is coplanar with a side edge of the semiconductor chip.
4. The semiconductor chip package of claim 1 wherein: the first dielectric layer contains a first plurality of holes, each of the first plurality of holes overlying one of the contact pads; a plurality of conductive traces extend from a location inside the first plurality of holes, respectively, each of the conductive traces being in electrical contact with one of the contact pads; a second dielectric layer contains a second plurality of holes, each of the second plurality of holes overlying one of the traces and being lined with a conductive layer in electrical contact with the trace; a plurality of first conductive bumps are formed in the second plurality of holes, respectively; each of the plurality of first conductive bumps extends through the encapsulant layer; and a plurality of second conductive bumps are formed on top of and in electric contact with the plurality of first conductive bumps, respectively.
5. The semiconductor chip package of claim 1 wherein the second conductive bump has a flat top portion that is coplanar with a surface of the encapsulant layer.
6. A semiconductor chip package comprising: a semiconductor chip having a plurality of contact pads; a first conductive bump in electrical contact with the contact pad; an nonconductive encapsulant layer overlying the semiconductor chip and surrounding the conductive bump, the first conductive bump extending through the encapsulant layer; and a second conductive bump on top of and in electric contact with the first conductive bump.
7. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is located directly over a side edge of the semiconductor chip.
8. The semiconductor chip package of claim 6 wherein a side edge of the encapsulant layer is coplanar with a side edge of the semiconductor chip.
Complete technical specification and implementation details from the patent document.
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Unknown
January 30, 2001
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