Reundancy circuit for semiconductor memories

1. In a semiconductor memory with word lines organized in segments, a segment select signal block, a word line select signal block, and a redundancy circuit with inter-segment redundancy for selecting a redundant word line upon an occurrence of a defective word line in one of the segments of the semiconductor memory, wherein the redundant word line is selected from the segment containing the defective word line or from a different segment, the improvement which comprises: a plurality of fuse sets assigned to respective said segments of the semiconductor memory, said fuse sets outputting fuse set output signals; a device connected to said fuse sets for evaluating the fuse set output signals and issuing segment select signals activating the redundant word line in the segment containing the defective word line or in the different segment based on the fuse set output signals thus evaluated; and a circuit connected to receive the fuse set output signals from said fuse sets, wherein, in the event of a correspondence between an applied row address and a fused address of said fuse set assigned to a given segment containing said redundant word line, said circuit activates a signal which is assigned to an address of the given segment, overwrites the regularly selected segment select signal generated from the row address in the segment select signal block, said circuit to receive the fuse set output signals further comprising a buffer at the output of each fuse set, each buffer receiving the output signals of the respective fuse set, whereby in the buffers a check is made to see whether it is necessary to use a redundant word line, which is the case when a fuse is activated.