Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations

1. A computer processor comprising: a plurality of execution units; a register file comprising: R read ports; W write ports; and N registers, with each register having 1 bit positions, wherein each bit position of each register is accessed by: R read lines, with each read line associated with one of the R read ports; W write lines, with each write line associated with one of the W write ports; a direction line that assumes a write direction state during a write operation and a read direction state during a read operation; C combined read/write word lines, with each combined read/write word line associated with one of the R read ports and one of the W write ports; and R-W read-only word lines if R>W, wherein each read-only word line is associated with one of the R read ports not associated with a combined read/write word line; or W-R write-only word lines if W>R, wherein each write-only word line is associated with one of the W write ports not associated with a combined read/write word line; wherein each of the 1 bit positions includes: a storage element for storing a value associated with the bit position; and a storage element multiplexer that selectively couples one of the R read lines to the storage element to read a value from the storage element when the direction line assumes the read direction state and one of the read-only or combined read/write word lines is asserted, wherein the read line selected is associated with the same read port as the asserted read-only or combined read/write word line, and selectively couples one of the W write lines to the storage element to write a value to the storage element when the direction line assumes the write direction state and one of the write-only or combined read/write word lines is asserted, wherein the write line selected is associated with the same write port as the asserted write-only or combined read/write word line; a bus of write lines coupled between the execution units and the register file; a bus of read lines coupled between the execution units and the register file; a multiplexer; a bus of register index select lines coupled between the execution units and the multiplexer; and a bus of direction lines, combined read/write word lines, and read-only word lines if R>W, or write-only word lines if W>R, coupled between the multiplexer and the register file.

2. The computer processor of claim 1 wherein each storage element includes a node that is coupled to the storage element multiplexer to receive a value from one of the W write lines via the storage element multiplexer during a write operation, and the node assumes a high-impedance state when the direction line assumes the write direction state.

3. The computer processor of claim 2 wherein the node is also coupled to the storage element multiplexer to provide a value to one of the R read line via the storage element multiplexer during a read operation, and the node assumes an active state based on the value stored in the storage element when the direction line assumes the read direction state.

4. The computer processor of claim 3 wherein the storage element powers down when the direction line assumes the write direction state, thereby causing the node to enter the high-impedance state.

5. The computer processor of claim 4 wherein each storage element comprises first and second inverters coupled into a feedback loop, and the node is derived from the output of either the first or second inverter.

6. The computer processor of claim 2 wherein each storage element includes a tri-state inverter having an output coupled to the node, and the output of the tri-state inverter enters the high-impedance state when tie direction line assumes the write direction state.

7. The computer processor of claim 6 wherein the storage element includes a second inverter, and the tri-state inverter and the second inverter are coupled into a feedback loop.