Circuit arrangement with a data sequence generator

1. Circuit arrangement with a data sequence generator (D) for generating an oscillator signal (sin a) as a sequence of digital data, wherein there is a first multiplication unit (M1) driven by a first auxiliary signal (h1) and a first control signal (sin c), where the first control signal (sin c) corresponds to the sine of a manipulated variable (c) that determines the frequency of the oscillator signal (sin a), a second multiplication unit (M2) driven by a second auxiliary signal (h2) and a second control signal (cos c), where the second control signal (cos c) corresponds to the cosine of the manipulated variable (c), a third multiplication unit (M3) driven by a third auxiliary signal (h3) and a third control signal (sin c+cos c), where the third control signal (sin c+cos c) corresponds to the sum of the first and second control signals (sin c, cos c), a first adding unit (A1) driven by the first multiplication unit (M1) and third multiplication unit (M3), a second adding unit (A2) driven by the first multiplication unit (M1) and the second multiplication unit (M2), a first time-delay unit (T1) driven by the first adding unit (A1), where the oscillator signal (sin a) is provided as third auxiliary signal (h3) at the output of the first time-delay unit (T1), a second time-delay unit (T2) driven by the second adding unit (A2), where the second auxiliary signal (h2) is provided at the output of the second time-delay unit (T2), a weighting unit (G) for weighting the third auxiliary signal (h3) with a factor of 2, a third adding unit (A3) driven by the second time-delay unit (T2) and the weighting unit (C), where the first auxiliary signal (h1) is provided at the output of the third adding unit (A3).

2. Circuit arrangement in accordance with claim 1, wherein there is a control unit (S) driven by a digital value corresponding to the manipulated variable (c) for the purpose of generating the control signals (sin c, cos c, sin c+cos c).

3. Circuit arrangement in accordance with claim 1, wherein there is an I/Q demodulator (M) for the I/Q demodulation of a complex input signal (e) which has a fourth multiplication unit (m4) driven by the first auxiliary signal (h1) and the imaginary part (Qp) of the input signal (e), has a fifth multiplication unit (M5) driven by the second auxiliary signal (h2) and the real part (Ip) of the input signal (e), has a sixth multiplication unit (M6) driven by the third auxiliary signal (h3) and the sum of the real part (Ip) and the imaginary part (Qp) of the input signal (e), has a fourth adding unit (A4) driven by the fourth multiplication unit (M4) and the sixth multiplication unit (M6), where the imaginary part (Q) of an out put signal (y) is provided at the output of the fourth adding unit (A4), and has a fifth adding unit (A5) driven by the fifth multiplication unit (M5) and the sixth multiplication unit (M6), where the real part (I) of the output signal (y) is provided at the output of the fifth adding unit (A5).

4. Circuit arrangement in accordance with claim 3, wherein there is a preprocessing unit (P) for generating the input signal (e) from serial input data bits (x).

5. Use of the circuit arrangement in accordance with claim 4 for the I/Q demodulation of continuous-phase-modulation (CPM), offset-quadrature-Phase-shift-keying (OQPSK), minimum-shift-keying (MSK) or Gaussian-minimum-shift-keying (GMSK) signals.