Method and apparatus for executing unresolvable system bus operations

1. An apparatus for processing system bus operations, the apparatus comprising: a plurality of processors each for executing instructions; memory for storing data; a system bus for transferring the stored data to the processors for execution, and for communicating operations to each of the processors; at least one cache associated with each one of the processors for processing snooped operations, the cache including: means for ensuring that each snooped operation is accepted for processing by each one of the processors by their at least one associated cache before each snooped operation is processed; wherein said snooped operation is presented to an associated one of said plurality of processors only when sufficient snooping resources are available in each of said at least one caches.

2. The apparatus of claim 1 wherein the means for ensuring includes: a plurality of snoopers for processing each snooped operation.

3. The apparatus of claim 2 wherein the means for ensuring includes: selection means for selecting one of the snoopers to process each one of the snooped operations.

4. The apparatus of claim 3 wherein the selection means includes: means for asserting a retry signal on the bus when all the snoopers are busy.

5. The apparatus of claim 4 wherein the snooper means includes: means for detecting when a retry is asserted on the bus for a received operation; and means for discarding the received operation upon the detection of the retry signal for the received operation.

6. The apparatus of claim 5 wherein the at least one cache includes: means for initiating an operation onto the system bus until all processors have accepted for processing the operation via their at least one cache.

7. In a multiprocessor computer having at least one cache associated with each one of the processors, a method of processing bus operations, the method comprising the steps of: detecting, by one of the caches, an operation issued from a processor associated with another of said caches; processing the detected operation by said associated processor only after each one of the other processors have indicated the same operation has been accepted for processing; wherein said processing occurs only when sufficient snooping resources are available in each of said at least one caches.

8. The method of claim 7 further comprising the step of: initiating an operation onto the system bus until all processors have indicated acceptance of the operation.

9. The method of claim 8 wherein the step of processing the detected operation includes the steps of: accepting the operation for processing without a transmitting a retry signal; and processing the operation only after it has been determined that no retry signal was transmitted for the operation for processing.

10. In a multiprocessor computer having at least one cache associated with each one of the processors, an apparatus for processing bus operations, the apparatus comprising: means for detecting, by one of the caches, an operation issued from a processor associated with another of said caches; means for processing the detected operation by said associated processors only after each one of the other processors have indicated the same operation has been accepted for processing; wherein said processing occurs only when sufficient snooping resources are available in each of said at least one caches.

11. The apparatus of claim 10 further comprising: means for initiating an operation onto the system bus until all processors have indicated the operation has been accepted for processing.

12. The apparatus of claim 11 further comprising: means for transmitting a retry signal whenever any cache is unable to accept an operation for processing.

13. The apparatus of claim 12 wherein the means for processing the detected operation includes: means for accepting the operation for processing without transmitting a retry signal; and means for processing the operation only after it has been determined that no retry signal was transmitted for the operation.

14. A method for processing system bus operations, comprising the steps of: executing instructions by a plurality of processors; storing data in a memory; transferring, by a system bus, the stored data to the processors for execution, and communicating operations to each of the processors; processing snooped operations by at least one cache associated with each one of the processors, said step of processing including ensuring that each snooped operation is accepted for processing by each one of the processors by their at least one associated cache before each snooped operation is processed; and presenting said snooped operation to an associated one of said plurality of processors only when sufficient snooping resources are available in each of said at least one caches.

15. The method of claim 14 wherein the step of ensuring includes the step of processing each snooped operation by a plurality of snoopers.

16. The method of claim 15 wherein the step of ensuring further includes the step of selecting one of the snoopers to process each one of the snooped operations.

17. The method of claim 16 wherein the step of selecting includes the step of asserting a retry signal on the bus when all the snoopers are busy.

18. The method of claim 17 wherein the step of processing each snooped operation includes the step of: detecting when a retry is asserted on the bus for a received operation; and discarding the received operation upon the detection of the retry signal for the received operation.

19. The method of claim 18 wherein the at least one cache performs the step of initiating an operation onto the system bus until all processors have accepted for processing the operation via their at least one cache.