Semiconductor memory circuit and redundancy control method

1. A semiconductor memory device having a plurality of non-redundant sense amplifiers, a plurality of non-redundant memory cells coupled to said non-redundant sense amplifiers, at least one redundant sense amplifier, and a plurality of redundant memory cells coupled to said at least one redundant sense amplifier, said redundant memory cells being used to replace defective memory cells among said non-redundant memory cells, comprising: a data bus with switchable data paths coupled to said non-redundant sense amplifiers and said at least one redundant sense amplifier; a driving circuit, coupled to said non-redundant sense amplifiers and said at least one redundant sense amplifier, that simultaneously activates both said at least one redundant sense amplifier and at least one of said non-redundant sense amplifiers; and a redundancy control circuit that receives an address signal, and that produces a switching signal having a value that depends on whether a defective memory cell is addressed by said address signal, wherein said data bus with switchable data paths comprises a first data bus, coupled to said non-redundant sense amplifiers, that transfers data read from said non-redundant memory cells and amplified by said non-redundant sense amplifiers, a second data bus, coupled to said at least one redundant sense amplifier, that transfers data read from said redundant memory cells and amplified by said at least one redundant sense amplifier, a third data bus that transfers data read in accordance with said address signal, and a switching circuit, coupled to said first, second and third data buses and to receive the switching signal from said redundancy control circuit, that selects one of said first and second data buses in accordance with the value of the switching signal and that transfers the data on the selected one of said first and second data buses to said third data bus, thereby redirecting access from the defective memory cell to a redundant memory cell when the defective memory cell is addressed.

2. The semiconductor memory circuit of claim 1, wherein said first and second data buses comprise a plurality of data bus lines that are switchably coupled to said at least one redundant sense amplifier and said non-redundant sense amplifiers in a certain order, and said switching circuit redirects access by omitting said at least one of said non-redundant sense amplifiers from said certain order.

3. The semiconductor memory circuit of claim 2, wherein said data bus has a plurality of data bus lines, said switching circuit comprises: a first plurality of switches coupling said data bus lines to said non-redundant sense amplifiers in a first order; and a second plurality of switches coupling said data bus lines to said non-redundant sense amplifiers and said at least one redundant sense amplifier in a second order, said second order being obtained by shifting said first order toward said at least one redundant sense amplifier, said redundancy control circuit comprising a redundancy programming circuit controlling said first plurality of switches and said second plurality of switches.

4. The semiconductor memory circuit of claim 3, further comprising a plurality of input-output buffers respectively coupled to said data bus lines, said first plurality of switches being disposed between said input/output buffers and said non-redundant sense amplifiers.

5. The semiconductor memory circuit of claim 3, further comprising a plurality of masking circuits respectively coupled to said data bus lines, said first plurality of switches being disposed between said masking circuits and said non-redundant sense amplifiers.

6. The semiconductor memory circuit of claim 1, wherein said driving circuit activates said non-redundant sense amplifiers selectively in response to said address signal.

7. The semiconductor memory circuit of claim 1, wherein said switching circuit redirects access from said memory cells coupled to a single one of said non-redundant sense amplifiers to said redundant memory cells coupled to said at least one redundant sense amplifier.

8. The semiconductor memory circuit of claim 1, wherein said switching circuit redirects access from said memory cells coupled to different ones of said non-redundant sense amplifiers to said redundant memory cells coupled to said at least one redundant sense amplifier.

9. The semiconductor memory circuit of claim 1, wherein the semiconductor memory circuit is a dynamic random-access memory circuit.

10. A method of controlling access to redundant memory cells and non-redundant memory cells, in a semiconductor memory device having a plurality of non-redundant sense amplifiers coupled to said non-redundant memory cells, at least one redundant sense amplifier coupled to said redundant memory cells, said redundant memory cells being used to replace defective memory cells among said non-redundant memory cells, and a data bus, said data bus including a first data bus that is coupled to said non-redundant sense amplifiers and that transfers data read from said non-redundant memory cells and amplified by said non-redundant sense amplifiers, a second data bus that is coupled to said at least one redundant sense amplifier and that transfers data read from said redundant memory cells and amplified by said at least one redundant sense amplifier, and a third data bus that transfers data read in accordance with the address signal, the method comprising: simultaneously activating both said at least one redundant sense amplifier and at least one of said non-redundant sense amplifiers; and switching data paths on said data bus, thereby redirecting access from a defective one of said non-redundant memory cells to one of said redundant memory cells, said switching data paths including producing a switching signal having a value which depends on whether a defective memory cell is addressed by an address signal, selecting one of said first and second data buses in accordance with the value of the switching signal, and transferring data on the selected one of said first and second data buses to said third data bus.

11. The method of claim 10, wherein each of said first and second data buses comprises a plurality of data bus lines, said switching data paths further comprises: disconnecting a first one of said data bus lines from a first of said non-redundant sense amplifiers coupled to a defective one of said non-redundant memory cells; connecting a second one of said data bus lines to a first of said at least one redundant sense amplifier coupled to one of said redundant memory cells; and shifting connections of said first one of said data bus lines and all of said data bus lines disposed between said first one of said data bus lines and said second one of said data bus lines away from said first of said non-redundant sense amplifiers and toward said first of said at least one redundant sense amplifier.

12. The method of claim 10, wherein the semiconductor memory device includes a redundancy control circuit having a redundancy programming circuit, the method further comprising: programming said redundancy programming circuit with addresses of defective memory cells; receiving said address signal; and comparing said address signal with addresses of defective memory cells.

13. The method of claim 12, wherein said simultaneously activating is carried out in response to said address signal.

14. The method of claim 11, wherein access to all of said non-redundant memory cells coupled to said first of said non-redundant sense amplifiers is redirected to said redundant memory cells that are coupled to said first of said at least one redundant sense amplifier.

15. The method of claim 11, wherein access to defective memory cells coupled to at least two different sense amplifiers among said sense amplifiers is redirected to said redundant memory cells that are coupled to said first of said at least one redundant sense amplifier.

16. A semiconductor memory device having a plurality of non-redundant sense amplifiers, a plurality of non-redundant memory cells coupled to the non-redundant sense amplifiers, at least one redundant sense amplifier, and a plurality of redundant memory cells coupled to the at least one redundant sense amplifier, the redundant memory cells being used to replace defective memory cells among the non-redundant memory cells, comprising: a data bus with switchable data paths coupled to the non-redundant sense amplifiers and the at least one redundant sense amplifier; a redundancy control circuit, coupled to said data bus and receiving an address signal, that switches the data paths when defective memory cells are addressed by the address signal, thereby redirecting access from the defective memory cells to the redundant memory cells; and a driving circuit, coupled to said non-redundant sense amplifiers and the at least one redundant sense amplifier, that simultaneously activates both the at least one redundant sense amplifier and at least one of the non-redundant sense amplifiers, when said redundancy control circuit redirects access from one of the defective memory cells coupled to the at least one of the non-redundant sense amplifiers to one of the redundant memory cells coupled to the at least one redundant sense amplifier, the data paths comprising a plurality of data bus lines that are switchably coupled to the at least one redundant sense amplifier and the non-redundant sense amplifiers in a certain order, said redundancy control circuit switches the data paths by omitting the at least one of the non-redundant sense amplifiers from the certain order.

17. The semiconductor memory circuit of claim 16, wherein the data bus has a plurality of data bus lines, said redundancy control circuit comprising: a first plurality of switches that couple the data bus lines to the non-redundant sense amplifiers in a first order; a second plurality of switches that couple the data bus lines to the non-redundant sense amplifiers and the at least one redundant sense amplifier in a second order, the second order being obtained by shifting the first order toward the at least one redundant sense amplifier; and a redundancy programming circuit that controls said first plurality of switches and said second plurality of switches, the semiconductor memory circuit further comprising a plurality of input-output buffers respectively coupled to the data bus lines, said first plurality of switches being disposed between said input-output buffers and the non-redundant sense amplifiers.

18. The semiconductor memory circuit of claim 16, wherein the data bus has a plurality of data bus lines, said redundancy control circuit comprising: a first plurality of switches that couple the data bus lines to the non-redundant sense amplifiers in a first order; a second plurality of switches that couple the data bus lines to the non-redundant sense amplifiers and the at least one redundant sense amplifier in a second order, the second order being obtained by shifting the first order toward the at least one redundant sense amplifier; and a redundancy programming circuit that controls said first plurality of switches and said second plurality of switches, the semiconductor memory circuit further comprising a plurality of masking circuits respectively coupled to the data bus lines, said first plurality of switches being disposed between said masking circuits and the non-redundant sense amplifiers.