Method and apparatus for using ATM queues for segmentation and reassembly of data frames

1. A method comprising: generating a data frame having data information at a processor; storing the data frame in a memory; providing the data frame to a processor interface having a segmentation engine and a direct memory access (DMA) engine; segmenting the data frame into a plurality of cells at the processor interface using the segmentation engine and the DMA engine; and injecting each of said cells into a cell input engine by transferring each of said cells to a number of memory locations by DMA transfer within a cell memory; and establishing a series of linked list pointers associated with said memory locations, wherein said series of linked list pointers includes a logical queue; wherein the number of memory locations is based on a length of the data frame.

2. A method as in claim 1 further comprising the step of transmitting said cells into a digital network in an order specified by said linked list pointers.

3. A digital switch comprising: a queuing circuit having a number of connection queues and class of service queues and configured to store a plurality of ATM cells, said cells including payload information and header information within said connection queues and said class of service queues based upon said header information; and a segmentation and reassembly (SAR) engine coupled to said queuing circuit and configured to extract cells from said queuing circuit that are bound for a local processor of said switch so as to preserve said payload information and to create and inject cells formed from data frames originated by said local processor into said queuing circuit; wherein said segmentation and reassembly engine includes a direct memory access (DMA) engine having a DMA channel, and a segmentation engine to segment a frame into a plurality of cells by using the DMA channel of the DMA engine, wherein the SAR engine is configured to input cells into the queuing circuit by transferring each of said cells to a number of memory locations by DMA transfer within a cell memory; and establishing a series of linked list pointers associated with said memory locations, wherein said series of linked list pointers includes a logical queue.

4. A digital switch as in claim 3 wherein said segmentation and reassembly engine is further configured to strip off said header information from said cells after extracting said cells.

5. A digital switch as in claim 4 wherein said segmentation and reassembly engine is further configured to perform error detection operations for frames of data reconstructed from extracted cells using payload information therefrom.

6. A digital switch as in claim 5 wherein said segmentation and reassembly engine is further configured to compute a CRC-32 value for use in said error detection operations.

7. A digital switch as in claim 6 wherein said segmentation and reassembly engine is further configured to overwrite the CRC-32 value for said reconstructed frames of data with a pass/fail flag according to said error detection operations.