Method for fabricating a polycide semiconductor device

1. A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a field oxide layer on a field region of the semiconductor substrate; forming a first polycide layer on the entire surface of the semiconductor substrate including the field oxide layer; selectively removing the first polycide layer, thereby forming a gate electrode and a lower electrode of a capacitor; successively forming a dielectric layer and a polysilicon layer on the entire surface including the lower electrode of the capacitor and patterning the dielectric layer and the lower electrode to form an upper electrode pattern of the capacitor and a resistor pattern; and forming an insulating layer on the resistor pattern; forming a second polycide layer on the upper electrode pattern of the capacitor.

2. The method as claimed in claim 1, wherein the process step of forming the lower electrode of the capacitor and the gate electrode comprises the steps of: forming a polysilicon layer and a metal layer on the entire surface of the semiconductor substrate including the field oxide layer; forming the polycide layer at interface of the polysilicon layer and the metal layer by an annealing process; and selectively etching the polysilicon layer and the polycide layer by using pattern masks for the lower electrode of the capacitor and the gate electrode so as to form the lower electrode of the capacitor on a predetermined area of the field oxide layer and the gate electrode on the semiconductor substrate of the active region.

3. The method as claimed in claim 2, wherein said metal layer is formed of any one of titanium, cobalt, or tungsten.

4. A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a field oxide layer on the semiconductor substrate; forming a first polysilicon layer and a first metal layer on the entire surface including the field oxide layer so as to form a first polycide layer on the first polysilicon layer by an annealing process; selectively etching the first polysilicon layer and the polycide layer to form a gate electrode and a lower electrode of a capacitor; forming a dielectric layer and a second polysilicon layer on the entire surface including the lower electrode of the capacitor and then successively removing the dielectric layer and the second polysilicon layer to form an upper electrode pattern of the capacitor and a resistor pattern; forming an insulating layer to cover the resistor pattern and forming sidewall spacers on both sides of the upper electrode pattern of the capacitor; and forming a second metal layer on the entire surface including the upper electrode pattern of the capacitor so as to form a second polycide layer on the semiconductor substrate at both sides of the gate electrode and on the upper electrode pattern of the capacitor by an annealing process.

5. The method as claimed in claim 4, wherein said polycide layer formed on the semiconductor substrate at both sides of the gate electrode is used as source and drain electrodes.

6. The method as claimed in claim 4, wherein an self-alignment process is applied to form the polycide layer on the semiconductor substrate at both sides of the gate electrode and on the upper electrode of the capacitor.

7. The method as claimed in claim 4, wherein said first and second metal layers are formed of any one of titanium, tungsten, or cobalt.

8. The method as claimed in claim 4, wherein said insulating layer is a high-temperature low-pressure dielectric layer.

9. The method as claimed in claim 4, wherein each of the metal layers where the polycide layer is not formed is removed after the annealing process.

10. The method as claimed in claim 4, after forming the gate electrode, further comprising the steps of: implanting lightly doped impurity ions into the semiconductor substrate at both sides of the gate electrode by using the gate electrode as a mask, so as to form LDD regions; and forming sidewall spacers on both sides of the gate electrode and then implanting heavily doped impurity ions to form source and drain impurity ions under surface of the semiconductor substrate at both sides of the gate electrode.

11. The method as claimed in claim 8, wherein said insulating layer serves to prevent the polycide from being formed.

12. A method for fabricating a semiconductor device on a semiconductor substrate, the method comprising the steps of: forming a field oxide layer on the semiconductor substrate; forming a first polysilicon layer and a first metal layer on the entire surface including the field oxide layer so as to form a first polycide layer on surface of the first polysilicon layer by an annealing process; selectively removing the first polysilicon layer and the polycide layer to form a gate electrode and a lower electrode of a capacitor; successively forming a dielectric layer and a second polysilicon layer on the entire surface including the lower electrode of the capacitor and then selectively removing the second polysilicon layer to form an upper electrode pattern of the capacitor and a resistor pattern; forming an insulating layer to cover the resistor pattern so as to form sidewall spacers on both sides of the upper electrode pattern of the capacitor; and depositing and then annealing a second metal on the entire surface including the upper electrode pattern of the capacitor so as to form a second polycide layer on surface of the upper electrode pattern of the capacitor.

13. The method as claimed in claim 12, wherein the polycide layer is not formed on the semiconductor substrate at both sides of the gate electrode because of the dielectric layer.

14. The method as claimed in claim 12, after forming the gate electrode, further comprising the steps of: implanting lightly doped impurity ions into the semiconductor substrate at both sides of the gate electrode by using the gate electrode as a mask, so as to form LDD regions; and forming sidewall spacers on both sides of the gate electrode and then implanting heavily doped impurity ions to form source and drain electrodes under surface of the semiconductor substrate at both sides of the gate electrode.

15. The method as claimed in claim 12, wherein the dielectric layer prevents the polycide layer from being formed on the gate electrode and on the semiconductor substrate at both sides of the gate electrode under the dielectric layer, and the insulating layer prevents the polycide layer from being formed on the polysilicon layer under the insulating layer.