Negative resistance memory cell and method

1. A memory cell comprising: a substrate including silicon; a first negative resistance device formed in a shallow trench and having first and second electrodes, the first electrode being coupled to a first reference voltage; a second negative resistance device formed on the substrate, the second negative resistance device having a first electrode coupled to a second reference voltage and a second electrode coupled to the second electrode of the first negative resistance device; and a switching element formed on the substrate and having a control electrode coupled to a first selection line, a first current-carrying electrode coupled to the second electrodes of the first and second negative resistance devices, and a second current-carrying electrode coupled to a second selection line.

2. The memory cell of claim 1 wherein the switching element comprises a MOS FET.

3. The memory cell of claim 1 wherein the substrate includes a p-type surface layer and the switching element comprises: a region of n-type silicon formed in the p-type surface layer; a first p+ silicon region formed in the n-type region; a second p+ region formed in the n-type region and spaced apart from the first p+ region; a gate oxide extending from the first p+ region to the second p+ region; and a gate formed on the gate oxide.

4. The memory cell of claim 3 wherein: the first negative resistance device comprises a tunnel diode formed in a shallow trench adjacent the first p+ region and is electrically coupled thereto by a conductor formed on a sidewall of the shallow trench; and the second negative resistance device comprises a tunnel diode formed within the first p+ region.

5. The memory cell of claim 1 wherein the substrate comprises p-type silicon.

6. The memory cell of claim 1 wherein the first and second negative resistance devices comprise tunnel diodes.

7. The memory cell of claim 1 wherein: the switching element comprises a MOS FET; the first negative resistance device comprises a tunnel diode that is formed in a shallow trench adjacent the MOS FET; and the second negative resistance device comprises a tunnel diode that is formed in a source or drain of the MOS FET.

8. The memory cell of claim 1 wherein the second reference voltage is more positive than the first reference voltage.

9. The memory cell of claim 1 wherein: the switching element comprises a PMOS FET; the substrate comprises p-type silicon; the first negative resistance device comprises a tunnel diode formed in a shallow trench adjacent the PMOS FET; the second negative resistance device comprises a tunnel diode formed in a drain of the PMOS FET; and the second reference voltage is more positive than the first reference voltage.

10. A memory device having an address bus and a data terminal, comprising: an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line; a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus; a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises: a first negative resistance device having a first electrode coupled to a first reference voltage and formed in a shallow trench; a second negative resistance device having a first electrode coupled to node that is coupled to a second electrode of the first negative resistance device and a second electrode coupled to a second reference voltage; and a switching element having a control electrode coupled to one of the word lines, a first current-carrying electrode coupled to the node and a second current-carrying electrode coupled to one of the bit lines, the first current-carrying electrode formed in the substrate adjacent the shallow trench.

11. The memory device of claim 10 wherein the memory device comprises a static random access memory.

12. The memory device of claim 10 wherein the first and second negative resistance devices comprise tunnel diodes.

13. The memory device of claim 10 wherein: the switching element comprises a MOS FET; the substrate comprises p-type silicon; the first negative resistance device comprises a tunnel diode formed in a shallow trench adjacent the MOS FET; the second negative resistance device comprises a tunnel diode formed in a drain of the MOS FET; and the second reference voltage is more positive than the first reference voltage.

14. The memory device of claim 10 wherein: the switching element comprises a PMOS FET; the first negative resistance device comprises a tunnel diode formed in a shallow trench adjacent the PMOS FET; and the second negative resistance device comprises a tunnel diode formed in a source or drain of the PMOS FET.

15. The memory device of claim 14 wherein the PMOS FET, the first tunnel diode and the second tunnel diode are formed in an area equal to six squares, where each side of each square is as long as a critical dimension of the device.

16. The memory device of claim 10 wherein the second reference voltage is less than one volt more positive than the first reference voltage.

17. The memory device of claim 10 wherein the substrate includes a p-type surface layer and the switching element comprises: a region of n-type silicon formed in the p-type surface layer; a first p+ region formed in the n-type region; a second p+ region formed in the n-type region and spaced apart from the first p+ region; a gate oxide extending from the first p+ region to the second p+ region; and a gate formed on the gate oxide.

18. The memory device of claim 17 wherein: the first negative resistance device comprises a tunnel diode formed in a shallow trench adjacent the first p+ region and electrically coupled to the first p+ region by a conductor formed on a sidewall of the shallow trench; and the second negative resistance device comprises a tunnel diode formed within the first p+ region.

19. A memory comprising: addressing means having a first set of terminals coupled to a first external port and a second set of terminals coupled to a memory array, the addressing means for targeting one or more memory cells within the memory array; and data conditioning means coupled to a second external port and to the memory array, the data conditioning means for reading data from or writing data to the one or more targeted memory cells, wherein each memory cell comprises: first negative resistance means having a first terminal coupled to a first reference voltage and a second terminal coupled to a node, the first negative resistance means formed in a shallow trench; second negative resistance means having a first terminal coupled to the node and a second terminal coupled to a second reference voltage; and switching means having a control electrode coupled to a first selection line, a first current-carrying electrode coupled to the node and a second current-carrying electrode coupled to a second selection line.

20. The memory of claim 19 wherein the memory comprises a SRAM.

21. The memory of claim 19 wherein the first negative resistance means comprises a tunnel diode having an anode coupled to the node and a cathode coupled to ground.

22. The memory of claim 19 wherein the second negative resistance means comprises a tunnel diode having a cathode coupled to the node and an anode coupled to a positive power supply voltage.

23. The memory of claim 19 wherein the switching means comprises a MOS FET.

24. The memory of claim 19 wherein the second reference voltage is less than one volt more positive than the first reference voltage.

25. The memory of claim 19 wherein the switching means, the first negative resistance means and the second negative resistance means are formed in an area equal to six squares, where each side of each square is as long as a critical dimension.

26. The memory of claim 19, further comprising a substrate including a p-type surface layer, wherein the switching element comprises: a region of n-type silicon formed in the p-type surface layer; a first p+ silicon region formed in the n-type region; a second p+ region formed in the n-type region and spaced apart from the first p+ region; a gate oxide extending from the first p+ region to the second p+ region; and a gate formed on the gate oxide.

27. The memory of claim 26 wherein the first negative resistance means comprises a tunnel diode formed in a shallow trench adjacent the first p+ region and electrically coupled to the first p+ region by a conductor formed on a sidewall of the shallow trench.

28. The memory of claim 27 wherein the second negative resistance means comprises a tunnel diode formed within the first p+ region.

29. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system; an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and a memory device coupled to the processor through the processor bus, the memory device comprising: at least one array of memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line; a row address circuit adapted to receive and decode a row address, and select a row of memory cells corresponding to the row address; a column address circuit adapted to couple the bit line for the column corresponding to a column address to an I/O line to receive or apply data to one of the memory cells in the selected row corresponding to a column address; and a data path circuit adapted to couple data between an external data terminal and each of the bit lines for respective columns, the data path circuit including a sense amplifier having an output coupled to the external data terminal of the memory device and an input, wherein each of the memory cells comprises first and second negative resistance devices formed from silicon and coupled together in series between first and second reference voltages and a switching device having a first current-carrying electrode coupled to a node between the first and second negative resistance devices, a control electrode coupled to one of the word lines and a second current-carrying electrode coupled to one of the bit lines.

30. The computer system of claim 29 wherein the memory device comprises a static random access memory.

31. The computer system of claim 29 wherein the first and second negative resistance devices each comprise a tunnel diode.

32. The computer system of claim 29 wherein the switching device comprises a MOS FET.

33. The computer system of claim 29 wherein the switching device comprises a MOS FET having a gate coupled to the control electrode, the first negative resistance device comprises a first tunnel diode having a cathode coupled to ground and an anode coupled to a node that is also coupled to a current-carrying electrode of the MOS FET and the second negative resistance device comprises a second tunnel diode having a cathode coupled to the node and an anode coupled to a voltage that is less than one volt more positive than ground.

34. The computer system of claim 29 wherein the switching device, the first negative resistance device and the second negative resistance device are formed in an area equal to six squares, where each side of each square is as long as a critical dimension.

35. A method of operating a memory device comprising: coupling a first voltage to a gate of a MOS FET that is part of a memory cell to turn the FET ON; and sensing a voltage at a node that is coupled to an anode of a first tunnel diode, a cathode of a second tunnel diode and a first current-carrying electrode of the MOS FET, the voltage representing a datum stored in the memory cell.

36. The method of claim 35, further comprising applying a voltage to the node to set the node to one of two stable states.

37. The method of claim 35, further comprising: applying a voltage to the node to set the node to one of two stable states; and coupling a second voltage to the gate of the MOS FET that is part of the memory cell to turn the MOS FET OFF.

38. The method of claim 35, further comprising: coupling a cathode of the first tunnel diode to a first reference voltage; and coupling a second reference voltage to an anode of the second tunnel diode.

39. The method of claim 35, further comprising: coupling a cathode of the first tunnel diode to a first reference voltage; and coupling a second reference voltage that is less than one volt more positive than the first reference voltage to an anode of the second tunnel diode.

40. A memory cell formed in a substrate, comprising: a switching element having a source/drain region; a first negative resistance device formed in a shallow trench adjacent to the switching element, the first negative resistance device having an electrode electrically coupled to the source/drain region of the switching element; and a second negative resistance device formed in the source/drain region of the switching element.

41. The memory cell of claim 40 wherein the first and second negative resistance devices comprise tunnel diodes.

42. The memory cell of claim 40 wherein the switching element comprises a PMOS transistor.

43. The memory cell of claim 40 wherein the first negative resistance device is formed vertically in the shallow trench.

44. The memory cell of claim 40 wherein the shallow trench abuts the source/drain region.

45. The memory cell of claim 44 wherein the electrode of the first negative resistance device is coupled to the source/drain region through the boundary between the shallow trench and the source/drain region.

46. The memory cell of claim 40 wherein the first negative resistance device includes a second electrode coupled to a first reference voltage and the second negative resistance device includes an electrode coupled to a second reference voltage.

47. The memory cell of claim 46 wherein the first reference voltage comprises a ground potential and the second reference voltage comprises a positive voltage.

48. An array of memory cells formed in a semiconductor substrate, comprising: a plurality of pairs of memory cells, each pair sharing a common sense node and formed in a common active region; and a plurality of shallow trenches formed in the substrate to isolate the active regions of the plurality of pairs of memory cells, wherein each memory cell of the pair includes a switch coupling a respective source/drain region to the common sense node, a first negative resistance device formed in the respective source/drain region, and a second negative resistance device having an electrode electrically coupled to the respective source/drain region, the second negative resistance devices of two adjacent pairs of memory cells formed in the shallow trench isolating the adjacent active regions.

49. The array of memory cells of claim 48 wherein the first and second negative resistance devices of each memory cell comprise tunnel diodes.

50. The array of memory cells of claim 48 wherein the switch of each memory cell comprises a PMOS transistor.

51. The array of memory cells of claim 48 wherein the second negative resistance device of each memory cell is formed vertically in the shallow trench.

52. The array of memory cells of claim 48 wherein the respective source/drain regions of each memory cell abuts a shallow trench.

53. The array of memory cells of claim 52 wherein the electrode of the second negative resistance device is coupled to the respective source/drain region through the boundary between the shallow trench and the respective source/drain region.