Method to fabricate self-aligned dual damascene structures

1. A method to form dual damascene structures in the fabrication of an integrated circuit device comprising: depositing a first etch stop layer overlying a semiconductor substrate layer; depositing a silicate glass layer overlying said first etch stop layer; depositing a second etch stop layer overlying said silicate glass layer; patterning said second etch stop layer thereby exposing the top surface of said silicate glass layer; depositing an hydrogen silsesquioxane layer overlying said second etch stop layer and said exposed silicate glass layer; depositing an oxide layer overlying said hydrogen silsesquioxane layer; patterning said oxide layer and said hydrogen silsesquioxane layer by reactive ion etching including N.sub.2 gas and thereby forming upper trenches; and etching away said silicate glass layer where not covered by said second etch stop layer using reactive ion etching not including N.sub.2 gas and thereby forming lower trenches wherein said lower trenches and overlying said upper trenches form said dual damascene structures.

2. The method according to claim 1 wherein semiconductor device structures, including gate electrodes and associated source and drain regions and a first level of metalization, are formed in and on said semiconductor substrate underlying an insulating layer and said first etch stop layer.

3. The method according to claim 1 wherein said silicate glass is fluorinated silicate glass deposited to a thickness of between about 5000 Angstroms and 7000 Angstroms.

4. The method according to claim 1 wherein said second etch stop layer comprises silicon oxynitride deposited to a thickness of between about 500 Angstroms and 600 Angstroms.

5. The method according to claim 1 wherein said hydrogen silsesquioxane layer is deposited to a thickness of between about 4000 Angstroms and 5000 Angstroms.

6. The method according to claim 1 wherein said patterning of said oxide layer and said hydrogen silsesquioxane layer thereby forming said upper trenches is accomplished by reactive ion etching using an etching recipe comprising between about 14 milliliters/second and 16 milliliters/second of C.sub.4 F.sub.8, between about 270 milliliters/second and 330 milliliters/second of CO, between about 360 milliliters/second and 440 milliliters/second of Ar, and between about 80 milliliters/second and 100 milliliters/second of N.sub.2.

7. The method according to claim 1 wherein said etching away of said silicate glass layer where not covered by said second etch stop layer and thereby forming said lower trenches is accomplished by reactive ion etching using an etching recipe comprising between about 14 milliliters/second and 16 milliliters/second of C.sub.4 F.sub.8, between about 270 milliliters/second and 330 milliliters/second of CO, and between about 360 milliliters/second and 440 milliliters/second of Ar.

8. The method according to claim 1 further comprising filling said dual damascene structures with a metal layer.

9. A method to form self-aligned dual damascene vias in the fabrication of an integrated circuit device comprising: providing first metal conductive traces through an insulating layer overlying a semiconductor substrate; depositing a first etch stop layer overlying said first metal conductive traces; depositing a silicate glass layer overlying said first etch stop layer; depositing a second etch stop layer overlying said silicate glass layer; patterning said second etch stop layer thereby exposing the top surface of said silicate glass layer to define areas of planned lower trenches wherein said areas overlie said first metal conductive traces; depositing an hydrogen silsesquioxane layer overlying said second etch stop layer and said silicate glass layer; depositing an oxide layer overlying said hydrogen silsesquioxane layer; patterning said oxide layer and said hydrogen silsesquioxane layer thereby forming said upper trenches having lateral widths of between about 0.4 microns and 0.5 microns wherein said upper trenches overlay said areas of planned lower trenches, wherein said etching away is accomplished by reactive ion etching including N.sub.2 gas; etching away said silicate glass layer where not covered by said second etch stop layer to said first etch stop layer and thereby forming said lower trenches having lateral widths of between about 0.3 microns and 0.5 microns, wherein said etching away is accomplished by reactive ion etching not including N.sub.2 gas; etching through said first etch stop layer to reveal the top surfaces of said first metal conductive traces and to complete said self-aligned dual damascene vias; depositing a second metal layer filling said lower trenches and said upper trenches and contacting said first metal conductive traces; and etching back said second metal layer to remove excessive metal above the top surface of said oxide layer to complete the fabrication of the integrated circuit device.

10. The method according to claim 9 wherein said silicate glass is fluorinated silicate glass deposited to a thickness of between about 5000 Angstroms and 6000 Angstroms.

11. The method according to claim 9 wherein said second etch stop layer comprises silicon oxynitride deposited to a thickness of between about 500 Angstroms and 600 Angstroms.

12. The method according to claim 9 wherein said hydrogen silsesquioxane layer is deposited to a thickness of between about 4000 Angstroms and 5000 Angstroms.

13. The method according to claim 9 wherein said patterning of said oxide layer and said hydrogen silsesquioxane layer thereby forming said upper trenches is accomplished by reactive ion etching using an etching recipe comprising between about 14 milliliters/second and 16 milliliters/second of C.sub.4 F.sub.8, between about 270 milliliters/second and 330 milliliters/second of CO, between about 360 milliliters/second and 440 milliliters/second of Ar, and between about 80 milliliters/second and 100 milliliters/second of N.sub.2.

14. The method according to claim 9 wherein said etching away of said silicate glass layer where not covered by said second etch stop layer and thereby forming said lower trenches is accomplished by reactive ion etching using an etching recipe comprising between about 14 milliliters/second and 16 milliliters/second of C.sub.4 F.sub.8, between about 270 milliliters/second and 330 milliliters/second of CO, and between about 360 milliliters/second and 440 milliliters/second of Ar.

15. The method according to claim 9 wherein said metal layer is copper.

16. A method to form self-aligned dual damascene vias in the fabrication of an integrated circuit device comprising: providing first metal conductive traces through an insulating layer overlying a semiconductor substrate; depositing a first silicon oxynitride layer overlying said first metal conductive traces; depositing a silicate glass layer overlying said first silicon oxynitride layer; depositing a second silicon oxynitride layer overlying said silicate glass layer; patterning said second silicon oxynitride layer thereby exposing the top surface of said silicate glass layer to define areas of planned lower trenches wherein said areas overlie said first metal conductive traces; depositing an hydrogen silsesquioxane layer overlying said second silicon oxynitride layer and said silicate glass layer; depositing an oxide layer overlying said hydrogen silsesquioxane layer; patterning said oxide layer and said hydrogen silsesquioxane layer thereby forming said upper trenches wherein said upper trenches overlay said areas of planned lower trenches, wherein said etching away is accomplished by reactive ion etching including N.sub.2 gas, and wherein said upper trenches have lateral widths of between about 0.4 microns and 0.6 microns; etching away said silicate glass layer where not covered by said second silicon oxynitride layer to said first silicon oxynitride layer and thereby forming said lower trenches, wherein said etching away is accomplished by reactive ion etching not including N.sub.2 gas and wherein said lower trenches have a lateral width of between about 0.3 microns and 0.5 microns; etching through said first silicon oxynitride layer to reveal the top surfaces of said first metal conductive traces and to complete said self-aligned dual damascene vias; depositing a second metal layer filling said lower trenches and said upper trenches and contacting said first metal conductive traces; and etching back said second metal layer to remove excessive metal above the top surface of said oxide layer to complete the fabrication of the integrated circuit device.

17. The method according to claim 16 wherein said second silicon oxynitride layer is deposited to a thickness of between about 500 Angstroms and 600 Angstroms.

18. The method according to claim 16 wherein said second metal layer is copper.