Pipe counter signal generator processing double data in semiconductor device

1. A pipe counter contained in a DDR SDRAM device, comprising: a controller for producing a counter control signal in response to rising and falling edge signals of an external clock signal; an enabling unit for producing a plurality of enable signals in response to the counter control signal and for enabling one of the enable signals during one period of the counter control signal; and a driver for receiving one of the enable signals, producing first and second pipe counter signals being synchronized with the rising and falling edge signals of the external clock signal, wherein one of the first and second pipe counter signals is activated during one period of the received enable signal.

2. The pipe counter as recited in claim 1, wherein the controller selects one from a plurality of clock signals being synchronized with the rising and falling edge signals of the external clock signal and produces the counter control signal by inverting a phase of the selected clock signal.

3. The pipe counter as recited in claim 1, wherein the enabling unit comprises: a binary counter including odd numbers of counting stages, which are, in series, coupled to each other, and wherein each counting stage includes a latch circuit and a transfer gate, wherein a high level signal from a final stage of the binary counter is transferred to a first stage of the binary counter and wherein an output from the first stage is propagated to the final stage whenever the counter control signal is activated; a latch circuit in parallel coupled to the final stage of the binary counter for latching an output from a previous stage; and an output means for outputting an output from the latch circuit and an output from each counting stage except for the final stage of the binary counter.

4. The pipe counter as recited in claim 1, wherein the driver comprises: a clock selection unit for receiving the rising and falling edge signals of the external clock signal from an external circuit, selecting one from the rising and falling edge signals and outputting the selected signal as a first clock signal or a second clock signal; a priority control signal latch unit for receiving and delaying the enable signals and outputting a modified pulse based on the enable signals, wherein the priority control signal latch unit receives and latches a priority control signal for selecting the rising edge signal or the falling edge signal of the external clock signal; and an output unit for outputting the first and second pipe counter signals in response to an output from the priority control signal latch unit when one of first and second clock signals is activated.