Digit line architecture for dynamic memory

1. A semiconductor device comprising: a multi-level digit line pair located on a portion of a semiconductor die, the multi-level digit line pair including a vertical twist at a location on the semiconductor die, the digit line pair having a first digit line and second digit line thereof vertically offset and vertically aligned on each side of the vertical twist at the location on the semiconductor die, first digit line and second digit line at the location on the semiconductor die of the multi-level digit line pair undergoing the vertical twist such that the first digit line is located below the second digit line on one horizontal side of the vertical twist at the location on the semiconductor die and located above the second digit line as an upper digit line on an opposite horizontal side of the vertical twist at the location on the semiconductor die.

2. The semiconductor device of claim 1, further comprising: a plurality of selectively addressable memory cells coupled to the multi-level digit line pair such that the plurality of selectively addressable memory cells is coupled to the first digit line and second digit line when the first digit line and second digit line are located below another digit line.

3. The semiconductor device of claim 2, wherein the first digit line and second digit line have an approximately equal number of selectively addressable memory cells coupled thereto.

4. The semiconductor device of claim 2, wherein the plurality of selectively addressable memory cells comprises a maximum area of six square feature size (6F.sup.2).

5. The semiconductor device of claim 2, wherein the plurality of selectively addressable memory cells comprises a maximum area of four square feature size (4F.sup.2).

6. The semiconductor device of claim 1, wherein the first digit line and second digit line are fabricated as a first vertically offset digit line and a second vertically offset digit line of one of a metal layer and a polysilicon layer.

7. The semiconductor device of claim 1, wherein the vertical twist includes a conductive contact extending through the semiconductor die to electrically connect portions of the first digit line and second digit line.

8. The semiconductor device of claim 7, wherein the conductive contact comprises one of a polysilicon plug and a metal plug.

9. The semiconductor device of claim 1, wherein the multi-level digit line pair includes a plurality of vertical twists therein.

10. An integrated circuit device comprising: an integrated circuit die having at least two vertically offset conductive levels; and a multi-level digit line pair located on a portion of the integrated circuit die, the multi-level digit line pair having a first electrically isolated digit line and a second electrically isolated digit line, the multi-level digit line pair including a vertical twist at a location on the integrated circuit die; each of the first digit line and the second digit line comprising a first section and a second section located in different conductive levels of the at least two vertically offset conductive levels and electrically connected; the first digit line and second digit line at the location on the integrated circuit die having at least a portion of the first section of the first digit line located vertically above the first section of the second digit line and vertically aligned therewith on one side of the vertical twist and having at least a portion of the second section of the first digit line located vertically below the second section of the second digit line and vertically aligned therewith on another side of the vertical twist.

11. The integrated circuit device of claim 10, further comprising: a conductive line connected between a vertically traversing electrical path and a section of a digit line of the first digit line and the second digit line, the conductive line located in a different conductive level than the first digit line and the second digit line.

12. The integrated circuit device of claim 10, further comprising: a plurality of selectively addressable memory cells coupled to the first digit line and second digit line such that the plurality of selectively addressable memory cells is coupled to the first digit line and second digit line when the first digit line and second digit line are located in a lower conductive level of the at least two vertically offset conductive levels.

13. The integrated circuit device of claim 12, wherein the first digit line and second digit line each have an approximately equal number of selectively addressable memory cells coupled thereto.

14. The integrated circuit device of claim 12, further comprising: isolation regions comprising isolation transistors located between the plurality of selectively addressable memory cells, each isolation transistor having a gate connected to a bias potential.

15. The integrated circuit device of claim 14, wherein the bias potential is negative.

16. The integrated circuit device of claim 10, further comprising an array of memory cells arranged in a cross point architecture.

17. The integrated circuit device of claim 10, further comprising: a plurality of selectively addressable memory cells having a maximum area of six square feature size (6F.sup.2) coupled to the multi-level digit line pair such that the plurality of selectively addressable memory cells is coupled to the first digit line and second digit line when the first digit line and second digit line are located in a lower conductive level of the at least two vertically offset conductive levels.

18. The integrated circuit device of claim 17, wherein the first digit line and second digit line each have an approximately equal number of selectively addressable memory cells coupled thereto.

19. The integrated circuit device of claim 10, further comprising: a plurality of selectively addressable memory cells having a maximum area of four square feature size (4F) coupled to the multi-level digit line pair such that the plurality of selectively addressable memory cells is coupled to the first digit line and second digit line when the first digit line and second digit line are located in a lower conductive level of the at least two vertically offset conductive levels.

20. The integrated circuit device of claim 10, wherein the first digit line and second digit line are fabricated as one of a metal layer and polysilicon layer.

21. The integrated circuit device of claim 10, wherein a vertically traversing electrical path comprises one of a metal plug and a polysilicon plug vertically extending through at least a portion of the integrated circuit die.

22. A semiconductor device comprising: a multi-level digit line pair located on a portion of a semiconductor die, the multi-level digit line pair having a first digit line and a second digit line vertically offset and vertically aligned at a location on the semiconductor die, the multi-level digit line pair at the location on the semiconductor die undergoing a vertical twist such that the first digit line is located below the second digit line and vertically aligned therewith on one horizontal side of the vertical twist and located above and vertically aligned with the second digit line as an upper digit line on an opposite horizontal side of the vertical twist at the location on the semiconductor die; and a plurality of addressable memory cells coupled to the multi-level digit line pair such that the plurality of addressable memory cells is coupled to the first digit line and the second digit line when the first digit line and the second digit line are located below another digit line of the multilevel digit line pair.

23. The semiconductor device of claim 22, further comprising isolation transistors fabricated between adjacent ones of the plurality of said addressable memory cells, each isolation transistor having a gate connected to a bias potential.