Direct memory access in a bridge for a multi-processor system

1. A bridge for a multi-processor system, the bridge comprising a first processor bus interface for connection to an I/O bus of a first processing set, a second processor bus interface for connection to an I/O bus of a second processing set, a device bus interface for connection to a device bus and a bridge control mechanism configured to be operable to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range.

2. The bridge of claim 1, wherein a different geographic address range is allocated to each of a plurality of device slots on the device bus.

3. The bridge of claim 1, wherein a different geographic address range is allocated to the processor set resources.

4. The bridge of claim 2, wherein the bridge control mechanism is configured to be responsive to the request for direct memory access from the device on the device bus to verify that an address supplied by a device falls within the correct geographic range for the slot in which the device is located.

5. The bridge of claim 4, wherein the bridge control mechanism includes an address decoding mechanism configured to be operable to maintain geographic address mappings, and to verify geographic addresses for direct memory access.

6. The bridge of claim 5, wherein geographic address mappings are configured in random access memory in the bridge.

7. The bridge of claim 5, wherein geographic address mappings are configured in a register in the bridge.

8. The bridge of claim 2, comprising a slot response register associated with each slot on the device bus, wherein the slot response register records ownership of a device by the first processing set, the second processing set or neither processing set.

9. The bridge of claim 8, wherein the bridge control mechanism is configured to be responsive to a direct memory access request from a device on the device bus to access the slot response register for the slot of the requesting device for identifying the owning processor set and for enabling access to the memory of the owning processor set.

10. The bridge of claim 9, wherein the slot response registers are configured in random access memory in the bridge.

11. The bridge of claim 9, wherein the slot response registers are configured in random access memory in the bridge.

12. The bridge of claim 1, comprising at least one further processor bus interface for connection to an I/O bus of a further processing set.

13. A bridge for a multi-processor system, the bridge comprising means for interfacing with a first I/O bus for a first processing set, a second I/O bus for a second processing set and a device bus, means providing geographic addressing for devices on the device bus and means responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range.

14. A computer system comprising a first processing set having a first I/O bus, a second processing set having a second I/O bus, a device bus with at least one device on the device bus and a bridge, the bridge being connected to the first I/O bus, the second I/O bus and the device bus, comprising a bridge control mechanism configured to be operable to provide geographic addressing for the device(s) on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range.

15. A computer system according to claim 14, wherein each processing set comprises at least one processor, memory and a processing set I/O bus controller.

16. The computer system of claim 15, wherein the resource is the processor set memory.

17. The computer system of claim 14, further comprising at least one further processing set.

18. The computer system of claim 14, comprising a plurality of switchable device slots, each device slot having a respective geographic address range associated therewith.

19. A method of operating a multi-processor system comprising a first processing set having a first I/O bus, a second processing set having a second I/O bus, a device bus with at least one device on the device bus and a bridge, the bridge being connected to the first I/O bus, the second I/O bus and device bus, the method comprising: maintaining respective geographic address ranges for the device(s) on the device bus; and responding to a request from a device on the device bus for direct memory access to a memory of a processing set to verify that an address supplied by a device falls within a correct geographic range.

20. The method of claim 19, comprising permitting direct memory access to proceed where the address falls within the correct geographic range and discarding a direct memory access request otherwise.