A two-step chemical mechanical polishing (CMP) process is provided for low dishing of metal lines in trenches in an insulation (oxide) layer, e.g., of silicon dioxide of a thickness of about 100-2000 nm, of a semiconductor wafer, e.g., of silicon, during its fabrication. The first step involves chemically mechanically polishing a metal layer, e.g., of copper of a thickness of about 200-2000 nm, disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing is effected at a high downforce, e.g., 3-8 psi, to remove at a high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches. The second step involves continuing the CMP at a lower downforce, e.g., 1-5 psi, to remove at a lower rate the lower portion of the metal layer with attendant minimized dishing to an extent for providing the metal lines as individual metal lines correspondingly disposed in the trenches. The total polishing time is about 120-48 seconds (2-8 minutes).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A chemical mechanical polishing process for low dishing of metal lines formed in trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprising: a first step of chemically mechanically polishing a metal layer disposed on the insulation layer and having a lower portion located in the trenches of the insulation layer for forming metal lines and an upper portion overlying the lower portion; the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches; and a second step of continuing the polishing at a selectively lower downforce sufficient to remove at a corresponding lower rate the lower portion of the metal layer with attendant minimized dishing to an extent for providing the metal lines as individual metal lines correspondingly disposed in the trenches.
2. The process of claim 1 wherein the first step is effected at a high downforce of about 3-8 psi, and the second step is effected at a lower downforce of about 1-5 psi, and wherein the total polishing time is about 120-480 seconds.
3. The process of claim 1 wherein the wafer comprises silicon, the insulation layer comprises silicon dioxide and the metal layer comprises copper.
4. The process of claim 1 wherein the insulation layer has a thickness of about 100-2000 nm and the metal layer has a thickness of about 200-2000 nm.
5. The process of claim 1 wherein the polishing is effected using a chemical mechanical polish comprising an alumina abrasive and ferric nitride as oxidizer.
6. The process of claim 1 wherein a liner layer forming an adhesion promoting diffusion barrier is disposed between the insulation layer and the metal layer.
7. The process of claim 6 wherein the wafer comprises silicon, the insulation layer comprises silicon dioxide, the metal layer comprises copper and the liner layer comprises tantalum/tantalum nitride.
8. The process of claim 6 wherein the insulation layer has a thickness of about 100-2000 nm, the metal layer has a thickness of about 200-2000 nm and the liner layer has a thickness of about 5-200 nm.
9. A chemical mechanical polishing process for low dishing of metal lines formed in trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprising: a first, bulk polishing, step of chemically mechanically polishing a semiconductor wafer defining a lower insulation layer containing a medial trench area having closely spaced apart trenches and a peripheral field area outwardly of the trench area, and an upper metal layer disposed on the insulation layer and extending across the field area and the trench area and forming corresponding closely spaced apart metal lines in the trenches, which lines are upwardly contiguous with an immediately overlying portion of the metal layer; the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high rate the portion of the metal layer extending across the field area and the trench area substantially without removing the portion of the metal layer immediately overlying the metal lines in the trenches and substantially without dishing of the portion of the metal layer forming the metal lines; and a second, overpolishing, step of continuing the polishing at a selectively lower downforce sufficient to overpolish the field area and to remove at a corresponding lower rate the portion of the metal layer immediately overlying the metal lines with attendant minimized dishing to an extent for providing the metal lines as individual metal lines unconnected to each other through the metal of the metal layer and correspondingly disposed in the trenches.
10. The process of claim 9 wherein the first step is effected at a high downforce of about 3-8 psi, and the second step is effected at a lower downforce of about 1-5 psi, and wherein the total polishing time is about 120-480 seconds.
11. The process of claim 9 wherein the wafer comprises silicon, the insulation layer comprises silicon dioxide and the metal layer comprises copper.
12. The process of claim 9 wherein the insulation layer has a thickness of about 100-2000 nm and the metal layer has a thickness of about 200-2000 nm.
13. The process of claim 9 wherein the polishing is effected using a chemical mechanical polish comprising an alumina abrasive and ferric nitride as oxidizer.
14. The process of claim 9 wherein a liner layer forming an adhesion promoting diffusion barrier is disposed between the insulation layer and the metal layer.
15. The process of claim 14 wherein the wafer comprises silicon, the insulation layer comprises silicon dioxide, the metal layer comprises copper and the liner layer comprises tantalum/tantalum nitride.
16. The process of claim 14 wherein the insulation layer has a thickness of about 100-2000 nm, the metal layer has a thickness of about 200-2000 nm and the liner layer has a thickness of about 5-200 nm.
17. A chemical mechanical polishing process for low dishing of copper lines formed in trenches in a silicon dioxide insulation layer of a silicon semiconductor wafer during fabrication thereof, comprising: a first, bulk polishing, step of chemically mechanically polishing a silicon semiconductor wafer defining a lower silicon dioxide insulation layer having a thickness of about 100-2000 nm and containing a medial trench area having closely spaced apart trenches and a peripheral field area outwardly of the trench area, an upper copper layer having a thickness of about 200-2000 nm and disposed on the insulation layer and extending across the field area and the trench area and forming corresponding closely spaced apart copper lines in the trenches, which lines are upwardly contiguous with an immediately overlying portion of the copper layer, and an intermediate liner layer forming an adhesion promoting diffusion barrier disposed between the insulation layer and the copper layer; the first step polishing being effected at a selectively high downforce of about 3-8 psi sufficient to remove at a corresponding high rate the portion of the copper layer extending across the liner layer, the field area and the trench area substantially without removing the portion of the copper layer immediately overlying the copper lines in the trenches and substantially without dishing of the portion of the copper layer forming the copper lines; and a second, overpolishing, step of continuing the polishing at a selectively lower downforce of about 1-5 psi sufficient to overpolish the liner layer and the field area and to remove at a corresponding lower rate the portion of the copper layer immediately overlying the copper lines with attendant minimized dishing to an extent for providing the copper lines as individual copper lines unconnected to each other through the copper of the copper layer and correspondingly disposed in the trenches; the first and second steps being effected at a minimized total polishing time of about 120-480 seconds.
18. The process of claim 17 wherein the liner layer comprises tantalum/tantalum nitride and has a thickness of about 5-200 nm.
19. The process of claim 17 wherein the polishing is effected using a chemical mechanical polish comprising an alumina abrasive and ferric nitride as oxidizer.
20. A chemical mechanical polishing process for low dishing of metal lines formed in trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprising: a first step of chemically mechanically polishing a metal layer disposed on the insulation layer and having a lower portion located in the trenches of the insulation layer for forming metal lines and an upper portion overlying the lower portion; the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches; and a second step of continuing the polishing at a selectively lower downforce which is at least about 20% less than the high downforce of the first step and sufficient to remove at a corresponding lower rate the lower portion of the metal layer with attendant minimized dishing to an extent for providing the metal lines as individual metal lines correspondingly disposed in the trenches; the first and second steps being effected so as to reduce both the amount of dishing and total polishing time.
21. A chemical mechanical polishing process for low dishing of metal lines formed in trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprising: a first step of chemically mechanically polishing a metal layer disposed on the insulation layer and having a lower portion located in the trenches of the insulation layer for forming metal lines and an upper portion overlying the lower portion; the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches; and a second step of continuing the polishing at a selectively lower downforce which is at least about 20% less than the high downforce of the first step and sufficient to remove at a corresponding lower rate the lower portion of the metal layer with attendant minimized dishing to an extent for providing the metal lines as individual metal lines correspondingly disposed in trenches; the first and second steps being effected so as to reduce the amount of dishing at a selective total polishing time.
22. A chemical mechanical polishing process for low dishing of metal lines formed in trenches in an insulation layer of a semiconductor wafer during fabrication thereof, comprising: a first step of chemically mechanically polishing a metal layer disposed on the insulation layer and having a lower portion located in the trenches of the insulation layer for forming metal lines and an upper portion overlying the lower portion; the first step polishing being effected at a selectively high downforce sufficient to remove at a corresponding high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches; and a second step of continuing the polishing at a selectively lower downforce which is at least about 20% less than the high downforce of the first step and sufficient to remove at a corresponding lower rate the lower portion of the metal layer with attendant minimized dishing to an extent for providing metal lines as individual metal lines correspondingly disposed in the trenches; the first and second steps being effected so as to reduce the total polishing time at a selective amount of dishing.
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March 23, 2000
May 8, 2001
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