A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A heterojunction bipolar transistor, comprising: (a) a collector made of a first III-V semiconductor material and with a surface having a crystal plane orientation of (100) within 0.5.degree.; (b) extrinsic base fingers on said collector and made of a second III-V semiconductor material, said fingers with sidewalls substantially perpendicular to said surface; (c) intrinsic base regions between said fingers and made of a third III-V semiconductor material; and (d) an emitter on said fingers and intrinsic base regions and made of a fourth III-V semiconductor material; (e) wherein said fourth III-V semiconductor material has a larger band gap than said third III-V semiconductor material.
2. The transistor of claim 1, wherein: (a) said first, second, and third III-V semiconductor materials are gallium arsenide containing dopants; and (b) said fourth III-V semiconductor material is aluminum gallium arsenide containing dopants.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 7, 1995
May 8, 2001
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