A cable drive circuit allows a transmitter in a process control system to drive signals across a capacitive length of cable. The cable drive circuit uses a charge pump to store charge, which is then used in conjunction with open drain outputs to transmit logic signals across a cable to a peripheral at the other end of the cable. A microcontroller or other device specifies the number of communication pulses to send across the cable before allowing the charge pump to recharge. By transmitting communication pulses for a small percentage of the time the average current is minimized, making the circuit suitable for operation under the 4-2OmA standard for two-wire devices.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An intrinsically safe drive circuit for driving digital signals across a cable between a fist location and a second location comprising: a first terminal for connection to a first digital signal; a second terminal connected to a first end of said cable with a second end of said cable connected to a device at said second location; pull up means connected to said second terminal; first transistor switching means connected to said second terminal, said switching means responsive to said first digital signal, said switching means pulling said second terminal to a first logic level when said switching means is turned on and said pull up means pulling said second terminal to a second logic level when said switching means is turned off; charge storage means connected to said pull up means, said charge storage means incrementally charging each time said pull up means pulls said second terminal to said second logic level; and control means for limiting said first digital signal to a first portion of a first period of time such that said charge storage means incrementally discharges during said first portion of said first period of time and does not incrementally discharge during a second portion of said first period of time allowing said charge storage means to recharge during said second portion of said first period of time.
2. Drive circuit of claim 1 wherein said charge storage means comprises: voltage supply means; current limiting means connected to said voltage supply means; capacitance means connected to said current limiting means; and voltage limiting means connected to said capacitance means.
3. Drive circuit of claim 2 wherein said cable has a length and a value of capacitance related to said length and said pull up means is selected so that a digital signal at said second terminal has a first rise time.
4. Drive circuit of claim 3 wherein said voltage limiting means comprises at least a single zener diode.
5. Drive circuit of claim 1 wherein said device includes second transistor switching means connected to said second end of said cable, said control means is selectively configurable for providing digital information during said first portion of said first period of time and for receiving digital information during a first portion of a second period of time, and said drive circuit further comprises logic circuit means coupled to said control means and to said second terminal with said control means setting said logic circuit means to pass said first digital signal from said control means to said second terminal during said first portion of said first period of time and to pass a second digital signal from said second terminal to said control means during said first portion of said second period of time; said charge storage means incrementally discharging during said first portion of said second period of time and not discharging during a second portion of said second period of time so that said charge storage device recharges during said second portion of said second period of time.
6. Drive circuit of claim 5 wherein said control means comprises a microcontroller.
7. Drive circuit of claim 5 wherein a combination of said first transistor switching means and said logic circuit means comprises a plurality of NAND gates.
8. Drive circuit of claim 3 wherein said first transistor switching means and said second transistor switching means comprise open drain transistors.
9. Drive circuit of claim 5 wherein said first location is at a first portion of a tank, said second location is at a second portion of said tank and said second digital signal is representative of a pressure at said second location.
10. An intrinsically safe drive circuit for driving digital signals across a cable between a fist location and a second location comprising: a first terminal for connection to a first digital signal; a second terminal connected to a first end of said cable with said second end of said cable connected to a device at said second location; pull up means connected to said second terminal; first transistor switching means connected to said second terminal, said first transistor switching means responsive to said first digital signal, said first transistor switching means pulling said second terminal to a first logic level when said first transistor switching means is turned on and said pull up means pulling said second terminal to a second logic level when said first transistor switching means is turned off; second transistor switching means connected to said device at said second end of said cable, said second transistor switching means responsive to an output signal from said device, said second transistor switching means pulling said second end of said cable to said first logic level when said switching means is turned on and said pull up means pulling said second end of said cable to said second logic level when said second transistor switching means is turned off; charge storage means connected to said pull up means, said charge storage means incrementally charging each time said pull up means pulls said second terminal to said second logic level; and control means selectively configurable for providing digital information during a first portion of a period of time and for receiving digital information during a first portion of a second period of time, said charge storage means incrementally discharging during said first portion of said first period of time, said charge storage means not discharging during a second portion of said first period of time and a second portion of said second period of time allowing said charge storage means to recharge during said second portion of said first period of time and said second portion of said second period of time; and logic circuit means coupled to said control means and to said second terminal with said control means setting said logic circuit means to pass said first digital signal from said control means to said second terminal during said first portion of said first period of time and to pass a second digital signal from said second terminal to said control means during said first portion of said second period of time.
11. Drive circuit of claim 10 where said charge storage means comprises: voltage supply means; current limiting means connected to said voltage supply means; capacitance means connected to said current limiting means; and voltage limiting means connected to said capacitance means.
12. Drive circuit of claim 11 wherein said cable has a length and a value of capacitance related to said length and said pull up means is selected so that a digital signal at said second has a first rise time.
13. Drive circuit of claim 12 wherein said voltage limiting means comprises at least a single zener diode.
14. Drive circuit of claim 10 wherein said control means comprises a microcontroller.
15. Drive circuit of claim 10 wherein a combination of said first transistor switching means and said logic circuit means comprises a plurality of NAND gates.
16. Drive circuit of claim 12 wherein said first transistor switching means and said second switching means comprise open drain transistors.
17. Drive circuit of claim 10 wherein a combination of said first transistor switching means and said logic circuit means comprises: a first open drain NAND gate having a first input connected to a first node of said control means, a second input connected through a first resistor to said pull up means, and an output connected to said second terminal; a second open drain NAND gate having a first input connected to said first terminal, a second input connected to said voltage supply means, and an output connected through said first resistor to said pull up means; a third open drain NAND gate having a first input connected to said second terminal, a second input connected to said voltage supply means, and an output connected through a second resistor to said pull up means; and a fourth open drain NAND gate having a first input connected to a second node of said control means, a second input connected through said second resistor to said voltage supply means, and an output connected to said first terminal, wherein said first node of said control means is at a logic high level and said second node of said control means is at a logic low level during said first portion of said first period of time, and wherein said first node of said control means is at a logic low level and said second node of said control means is at a logic high level during said first portion of said second period of time.
18. Drive circuit of claim 10 wherein said first location is at a first portion of a tank, said second location is at a second portion of said tank and said second digital signal is representative of a pressure at said second location.
19. An intrinsically safe drive circuit for driving digital signals across a cable between a first location and a second location comprising: a first terminal for connection to a first digital signal; a second terminal connected to a first end of said cable with said second end of said cable connected to a device at said second location; pull up means connected to said second terminal; charge storage means connected to said pull up means; first transistor switching means connected to said second terminal, said first transistor switching means responsive to said first digital signal, said first transistor switching means pulling said second terminal to a first logic level when said first transistor switching means is turned on and said pull up means pulling said second terminal to a second logic level when said first transistor switching means is turned off; second transistor switching means connected to said device at said second end of said cable, said second transistor switching means responsive to an output signal from said device, said second transistor switching means pulling said second end of said cable to said first logic level when said switching means is turned on and said pull up means pulling said second end of said cable to said second logic level when said second transistor switching means is turned off; control means selectively configurable for providing digital information during a first portion of a period of time and for receiving digital information during a first portion of a second period of time; logic circuit means coupled to said control means and to said second terminal with said control means setting said logic circuit means to pass said first digital signal from said control means to said second terminal during said first period of time and to pass a second digital signal from said second terminal to said control means during said second period of time, said first transistor means in combination with said logic circuit means includes, a first open drain NAND gate having a first input connected to a first node of said control means, a second input connected through a first resistor to said pull up means, and an output connected to said second terminal; a second open drain NAND gate having a first input connected to said first terminal, a second input connected to said voltage supply means, and an output connected through said first resistor to said pull up means; a third open drain NAND gate having a first input connected to said second terminal, a second input connected to said voltage supply means, and an output connected through a second resistor to said pull up means; and a fourth open drain NAND gate having a first input connected to a second node of said control means, a second input connected through said second resistor to said voltage supply means, and an output connected to said first terminal, wherein said first node of said control means is at a logic high level and said second node of said control means is at a logic low level during said first period of time, and wherein said first node of said control means is at a logic low level and said second node of said control means is at a logic high level during said second period of time.
20. An arrangement for driving digital signals trough a cable comprising: a terminal coupled to the cable; a storage device coupled to the terminal; and, a controller coupled to the terminal, wherein the controller is arranged to control the terminal between first and second states so as to drive the digital signals through the cable, when the storage device discharges into the controller when the terminal is in the first state, wherein the storage device drives the cable when the terminal is in the second state, and wherein the controller is arranged to periodically inhibit the terminal having the first state for sufficient time to permit the storage device to recharge.
21. The arrangement of claim 20 wherein the controller is a logic circuit.
22. The arrangement of claim 20 wherein the storage device includes a first impedance coupling the storage device to a source and a second impedance coupling the storage device to the terminal.
23. The arrangement of claim 20 wherein the cable has first and second ends, wherein the first end of the cable is coupled to the terminal, wherein the second end of the cable is coupled to a sensor, and wherein the sensor is arranged to drive the second end of the cable between the first and second states so as to transmit information to the controller.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 23, 1997
May 15, 2001
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