A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for making a transistor comprising: providing a silicon substrate comprising a silicon-germanium epitaxial layer; forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer; implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region; removing the masking implant layer after the implanting to expose the channel region; forming a silicon epitaxial layer on the exposed channel region; converting at least a portion of the silicon epitaxial layer to silicon oxide to define a gate dielectric layer for the transistor; and forming a conductive gate on the gate dielectric layer.
2. A method according to claim 1, wherein converting comprises converting only a portion of the silicon epitaxial layer to the silicon oxide so that a silicon protection layer remains between the gate dielectric layer and the channel region.
3. A method according to claim 2, wherein the silicon protection layer has a thickness in a range of about 0.5 to 2.5 nm.
4. A method according to claim 1, wherein converting comprises converting 75 to 95% of a thickness of the silicon epitaxial layer into the silicon oxide.
5. A method according to claim 1, wherein the silicon epitaxial layer has a thickness in a range of about 0.5 to 3 nm.
6. A method according to claim 1, wherein the silicon-germanium epitaxial layer comprises about 30 to 60% germanium by weight percentage.
7. A method according to claim 1, further comprising annealing the silicon substrate comprising the silicon-germanium epitaxial layer before forming the silicon epitaxial layer on the exposed channel region.
8. A method according to claim 1, wherein the masking implant layer comprises polysilicon.
9. A method according to claim 1, wherein forming the silicon epitaxial layer is performed at a temperature less than about 600.degree. C.
10. A method according to claim 1, wherein converting is performed using plasma enhanced chemical vapor deposition (PECVD).
11. A method according to claim 10, wherein the PECVD is performed at a temperature less than about 600.degree. C.
12. A method according to claim 1, wherein converting is performed using oxidation at a pressure in a range of about 5 to 25 atmospheres.
13. A method according to claim 12, wherein the oxidation is performed at a temperature less than about 700.degree. C.
14. A method for making a transistor comprising: forming a masking implant layer on a channel region of a silicon-germanium epitaxial layer on a silicon substrate; implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region; removing the masking implant layer after the implanting to expose the channel region; forming a silicon epitaxial layer on the exposed channel region; and converting only a portion of the silicon epitaxial layer to silicon oxide to define a gate dielectric layer for the transistor, the gate dielectric layer comprising a gate oxide layer and a silicon protection layer between the gate oxide layer and the channel region.
15. A method according to claim 14, further comprising forming a conductive gate on the gate oxide layer.
16. A method according to claim 14, wherein converting comprises converting 75 to 95% of a thickness of the silicon epitaxial layer into the silicon oxide.
17. A method according to claim 14, wherein the silicon protection layer has a thickness in a range of about 0.5 to 2.5 nm.
18. A method according to claim 14, wherein the silicon epitaxial layer has a thickness in a range of about 0.5 to 3 nm.
19. A method according to claim 14, wherein the silicon-germanium epitaxial layer comprises 30 to 60% germanium by weight percentage.
20. A method according to claim 14, further comprising annealing the silicon-germanium epitaxial layer on the silicon substrate before forming the silicon epitaxial layer on the exposed channel region.
21. A method according to claim 14, wherein the masking implant layer comprises polysilicon.
22. A method according to claim 14, wherein forming the silicon epitaxial layer is performed at a temperature less than about 600.degree. C.
23. A method according to claim 14, wherein converting is performed using plasma enhanced chemical vapor deposition (PECVD).
24. A method according to claim 23, wherein the PECVD is performed at a temperature less than about 600.degree. C.
25. A method according to claim 14, wherein converting is performed using oxidation at a pressure in a range of about 5 to 25 atmospheres.
26. A method according to claim 25, wherein the high pressure oxidation is performed at a temperature less than about 700.degree. C.
27. A method for making a transistor comprising: providing a silicon substrate comprising a silicon-germanium epitaxial layer comprising 30 to 60% germanium by weight percentage; forming a polysilicon layer on a channel region of the silicon-germanium epitaxial layer; implanting dopants into the silicon-germanium epitaxial layer using the polysilicon layer to define spaced apart source and drain regions adjacent the channel region; removing the polysilicon layer after the implanting to expose the channel region; forming a silicon epitaxial layer on the exposed channel region; converting 75 to 95% of a thickness of the silicon epitaxial layer into silicon oxide to define a gate oxide layer, the remaining silicon epitaxial layer forming a silicon protection layer between the gate oxide layer and the channel region; and forming a conductive gate on the gate oxide layer.
28. A method according to claim 27, wherein the silicon protection layer has a thickness in a range of about 0.5 to 2.5 nm.
29. A method according to claim 27, wherein the silicon epitaxial layer has a thickness in a range of about 0.5 to 3 nm.
30. A method according to claim 27, further comprising annealing the silicon substrate comprising the silicon-germanium epitaxial layer before forming the silicon epitaxial layer on the exposed channel region.
31. A method according to claim 27, wherein forming the silicon epitaxial layer is performed at a temperature less than about 600.degree. C.
32. A method according to claim 27, wherein converting is performed using plasma enhanced chemical vapor deposition (PECVD).
33. A method according to claim 32, wherein the PECVD is performed at a temperature less than about 600.degree. C.
34. A method according to claim 27, wherein converting is performed using oxidation at a pressure in a range of about 5 to 25 atmospheres.
35. A method according to claim 34, wherein the oxidation is performed at a temperature less than about 700.degree. C.
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August 16, 1999
May 22, 2001
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