A method and arrangement for forming a local interconnect without weakening the field edge or disconnecting the diffusion region at the field edge provides an etch stop layer with increased hardness in comparison to conventional etch stop layers, such as plasma enhanced chemical vapor deposition (PECVD) SiON etch stop layers. A PECVD process is used to deposit silicon carbide (SiC). The increased hardness of the SiC etch stop layer is slower to etch than conventional PECVD SiON so that when etching the dielectric layer in which the local interconnect material is subsequently deposited, the etching stops at the etch stop layer in a controlled manner. This prevents the unintentional etching of the silicide region and diffusion region at the field edge.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a local interconnect, comprising the steps of: forming devices on a semiconductor wafer; forming silicide regions on the devices; depositing a silicon carbide etch stop layer over the devices and the silicide regions; depositing a dielectric layer on the etch stop layer; etching the dielectric layer in accordance with a desired pattern to form a local interconnect opening with an etchant chemistry that is selective to the etch stop layer; etching the etch stop layer in accordance with a desired pattern with an etchant chemistry that is selective to the silicide regions; and depositing conductive material in the local interconnect opening.
2. The method of claim 1, wherein the step of depositing the silicon carbide etch stop layer comprises performing plasma enhanced chemical vapor deposition (PECVD).
3. The method of claim 2, wherein the step of depositing the silicon carbide etch stop layer comprises supplying H.sub.2 and C.sub.3 H.sub.8 and SiH.sub.4 as reactant gases to a deposition chamber.
4. The method of claim 3, wherein the step of depositing a dielectric layer on the silicon carbide etch stop layer comprises depositing silicon dioxide derived from tetraethyl orthosilicate.
5. A local interconnect arrangement comprising: a substrate layer; semiconductor devices on the substrate; silicide regions on the semiconductor devices; a silicon carbide etch stop layer on portions of some of the silicide regions; a dielectric layer on the etch stop layer; a local interconnect opening extending through the dielectric layer and the etch stop layer to at least one of the silicide regions; and conductive material filling the local interconnect opening and contacting at least one of the silicide regions.
6. The arrangement of claim 5, wherein the silicon carbide etch stop layer comprises plasma enhanced chemical vapor deposition (PECVD) silicon carbide.
7. The arrangement of claim 6, wherein the dielectric layer comprises silicon dioxide derived from tetraethyl orthosilicate.
8. A method of increasing the selectivity of etchants with respect to an etch stop layer, comprising the steps of: forming a silicide region; depositing a silicon carbide containing etch stop layer on the silicide regions; and forming a dielectric layer on the etch stop layer, wherein the etch rate of the etch stop layer is substantially slower than the etch rate of the dielectric layer when exposed to a first etchant chemistry, and the etch rate of the silicide region is substantially slower than the etch rate of the etch stop layer when exposed to a second etchant chemistry.
9. The method of claim 8, wherein the step of depositing the silicon carbide containing etch stop layer includes plasma enhanced chemical vapor deposition (PECVD) of the silicon carbide.
10. The method of claim 9, wherein the step of depositing the silicon carbide etch stop layer comprises supplying H.sub.2 and C.sub.3 H.sub.8 and SiH.sub.4 as reactant gases to a deposition chamber.
11. The method of claim 10, wherein the step of depositing a dielectric layer on the silicon carbide etch stop layer comprises depositing silicon dioxide derived from tetraethyl orthosilicate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 30, 1999
May 22, 2001
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