A system for generating voltages on an integrated circuit utilizes an overlapping clocking scheme. An oscillator generates the overlapping clock signals, which are coupled through oscillator buffers, to row pumps. In response to the overlapping clock signals, row pumps generate high voltages, typically higher than the VDD voltage of the integrated circuit. These high voltages may be used to program programmable memory cells or interface to logic components of the integrated circuit.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for generating a voltage on an integrated circuit comprising: generating a first clock signal; generating a second clock signal, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; charging a first node using the first clock signal; charging a second node using the second clock signal; and generating the voltage on the integrated circuit at a third node using a charge at the second node.
2. The method of claim 1 wherein charging the first node comprises coupling the first clock signal through a first capacitor to the first node.
3. The method of claim 2 wherein the first capacitor is a native device transistor, the native device transistor having a threshold voltage less than an enhancement transistor on the integrated circuit.
4. The method of claim 1 wherein charging the second node comprises: coupling the second clock signal through a capacitor to the second node; and transferring a charge from the first node to the second node.
5. The method of claim 1 wherein generating the voltage at the third node comprises transferring the charge from the second node to the third node.
6. The method of claim 1 further comprising: coupling the third node to a floating gate of a transistor; and programming the transistor using the voltage at the third node.
7. The method of claim 1 wherein a falling edge of the second clock signal follows a falling edge of the first clock signal.
8. The method of claim 1 wherein the first clock signal is generated by a ring oscillator.
9. The method of claim 1 wherein the first clock signal is generated from a first position of a ring oscillator and the second clock signal is generated from a second position of the ring oscillator, wherein the first position and the second position are separated by at least two buffer stages in the ring oscillator.
10. The method of claim 1 wherein the rising edge of the second clock signal occurs at approximately a center of the pulse width of the first clock signal.
11. A method for generating a voltage on an integrated circuit comprising: generating a first clock signal, the first clock signal alternating between a first voltage level and a second voltage level, the first voltage level above the second voltage level; generating a second clock signal, the second clock signal alternating between a third voltage level substantially equal to the first voltage level and a fourth voltage level substantially equal to the second voltage level, the third voltage level above the fourth voltage level, and wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; charging a first node using the first clock signal; and generating the voltage on the integrated circuit by producing a fifth voltage level at a second node using the second clock signal and a charge at the first node, wherein the fifth voltage level is above the first voltage level and the third voltage level.
12. A method for generating a voltage on an integrated circuit comprising: producing a first clock signal alternating between a first voltage level and a second voltage level, the first voltage level above the second voltage level; producing a second clock signal alternating between a third voltage level substantially equal to the first voltage level and a fourth voltage level substantially equal to the second voltage level, the third voltage level above the fourth voltage level, and wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; coupling the first clock signal and the second clock signal to a voltage pump; and generating the voltage on the integrated circuit by producing a fifth voltage level at an output node of the voltage pump using the first and second clock signals, wherein the fifth voltage level is above the first voltage level and the third voltage level.
13. A method for generating a voltage on an integrated circuit comprising: generating a first clock signal; generating a second clock signal, wherein a rising edge of the second clock signal occurs when a portion of the first clock signal is at a logic high; charging a first node using the first clock signal; charging a second node using the second clock signal; and generating the voltage on the integrated circuit at a third node using a charge at the second node.
14. A method for generating a voltage on an integrated circuit comprising: generating a first clock signal; generating a second clock signal, wherein the second clock signal is overlapping with the first clock signal and is out-of-phase with a rising edge of the first clock signal; charging a first node using the first clock signal; charging a second node using the second clock signal; generating the voltage on the integrated circuit at a third node using a charge at the second node.
15. An apparatus for generating a voltage on an integrated circuit comprising: a clock generator, generating a first clock signal and a second clock signal operating between a first voltage level and a second voltage level, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; and a voltage pump, coupled to the first clock signal and the second clock signal, the voltage pump configured to generate the voltage on the integrated circuit by generating a third voltage level at an output node, wherein the third voltage level is above the first voltage level and the second voltage level.
16. The apparatus of claim 15 wherein the clock generator is an oscillator comprising an odd number of stages, wherein the first clock signal is produced at one position of the oscillator, and the second clock signal is produced at a different position of the oscillator.
17. The apparatus of claim 15 wherein the voltage pump comprises: a first capacitor coupled to the first clock signal and a first node, wherein the first node is charged by the first capacitor and the first clock signal; and a second capacitor coupled to the second clock signal and to a second node, wherein the second node is charged by the second capacitor, the second clock signal, and by the charge at the first node, and wherein the charge at the second node generates the third voltage level at the output node.
18. The apparatus of claim 15 further comprising an oscillator buffer that buffers the first clock signal and the second clock signal to said voltage pump.
19. The apparatus of claim 15 wherein a shift register is coupled to the voltage pump, the shift register indicates a row of programmable cells to configure using the voltage pump.
20. A programmable logic device comprising the apparatus of claim 15.
21. An apparatus for generating a voltage on an integrated circuit comprising: a first clock generator, generating a first clock signal alternating between a first voltage level and a second voltage level; a second clock generator, generating a second clock signal alternating between a third voltage level substantially equal to the first voltage level and a fourth voltage level substantially equal to the second voltage level, and wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; and a voltage pump, coupled to the first clock signal and the second clock signal, the voltage pump configured to generate the voltage on the integrated circuit by generating a fifth voltage level at an output node of the integrated circuit, wherein the fifth voltage level is above the first, second, third, and fourth voltage levels.
22. A programmable logic device comprising the apparatus of claim 21.
23. An integrated circuit comprising: a clock generator, generating a first clock signal and a second clock signal, wherein a rising edge of the second clock signal occurs when a portion of the first clock signal is at a logic high; and a voltage pump, coupled to the first clock signal and the second clock signal, the voltage pump configured to charge a first node using the first clock signal, and to generate a voltage level at a second node by charging the second node using the second clock signal and the charge at the first node, wherein the voltage level at the second node is above a maximum voltage level of the first clock signal and a maximum voltage level of the second clock signal.
24. A programmable logic device comprising the integrated circuit of claim 23.
25. A voltage pump circuit in an integrated circuit comprising: a first signal source producing a first clock signal; a second signal source producing a second clock signal overlapping with the first clock signal; and a voltage pump, coupled to receive the first clock signal and the second clock signal, the voltage pump comprising: a first capacitor, coupled to a first node and to the first clock signal; a second capacitor, coupled to a second node and to the second clock signal; a first transistor, coupled between the first node and a high voltage node, wherein a gate of the first transistor is coupled to an output node; a second transistor, coupled between the high voltage node and the output node, wherein a gate of the second transistor is coupled to the output node; a third transistor, coupled between the first node and the second node, wherein a gate of the third transistor is coupled to the first node; and a fourth transistor, coupled between the second node and the output node, wherein a gate of the fourth transistor is coupled to the second node.
26. A system for generating a voltage on an integrated circuit comprising: a first signal source producing a first clock signal; a second signal source producing a second clock signal, wherein a rising edge of the second clock signal occurs when a portion of the first clock signal is a logic high; and a voltage pump, coupled to the first clock signal source and the second clock signal source, wherein a charge generated at a first node using the first clock signal is used to boost a charge generated at a second node using the second clock signal, the second node providing the voltage.
27. An integrated circuit comprising: a clock generator, generating a first clock and a second clock, wherein a rising edge of the second clock occurs when a portion of said first clock signal is a logic high; an inversion buffer, coupled to the clock generator, the inversion buffer generating a third clock signal and a fourth clock signal, wherein the third clock signal is out-of-phase with the first clock signal and the fourth clock signal is out-of-phase with the second clock signal; a first voltage pump generating a first relatively consistent voltage output, wherein a first stage of the first voltage pump is coupled to the first clock signal and a second stage of the first voltage pump is coupled to the second clock signal; and a second voltage pump generating a second relatively consistent voltage output, wherein a first stage of the second voltage pump is coupled to the third clock signal and a second stage of the second voltage pump is coupled to the fourth clock signal.
28. The integrated circuit of claim 27 further comprising a plurality of programmable memory cells, wherein the first voltage output is coupled to a first row of the plurality of programmable memory cells and the second voltage output is coupled to a second row of the plurality of programmable memory cells.
29. The integrated circuit of claim 27 wherein the first voltage pump comprises: a first capacitor in the first stage; and a second capacitor in the second stage.
30. The integrated circuit of claim 27 wherein the clock generator is a ring oscillator.
31. A programmable logic device comprising the integrated circuit of claim 27.
32. A system on an integrated circuit comprising: a clock generator, generating a first clock and a second clock operating between a first voltage level and a second voltage level, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; an inversion buffer, coupled to receive the first clock signal and the second clock signal and to generate a third clock signal and a fourth clock signal operating between a third voltage level substantially equal to the first voltage level and a fourth voltage level substantially equal to the second voltage level, wherein the third clock signal is out-of-phase with the first clock signal and the fourth clock signal is out-of-phase with the second clock signal; a first voltage pump, including a first stage coupled to the first clock signal and a second stage coupled to the second clock signal, wherein the first voltage pump generates a voltage at a fifth voltage level at a first output node, and wherein the fifth voltage level is above the first voltage level and the second voltage level; and a second voltage pump, including a first stage coupled to the third clock signal and a second stage coupled to the fourth clock signal, wherein the second voltage pump generates a voltage at a sixth voltage level at a second output node, and wherein the sixth voltage level is above the third voltage level and the fourth voltage level.
33. A programmable logic device comprising the system of claim 32.
34. The system of claim 32 further comprising a plurality of memory cells, and wherein a first row of memory cells from the plurality of memory cells is coupled to the first output node, and a second row of memory cells from the plurality of memory cells is coupled to the second output node.
35. A programmable logic integrated circuit comprising: a plurality of pads, wherein a first pad is coupled to a first voltage supply at a first voltage level, and wherein a second pad is coupled to a second voltage supply at a second voltage level; and a voltage generator circuit coupled to the first pad and the second pad, the voltage generator circuit comprising: a clock generator, generating a first clock signal and a second clock signal operating between a third voltage level and a fourth voltage level, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; and a voltage pump, coupled to the first clock signal and the second clock signal, the voltage pump configured to generate a fifth voltage level at an output node, wherein the fifth voltage level is above the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level.
36. The programmable logic integrated circuit of claim 35 further comprising a plurality of programmable memory cells, wherein the output node is coupled to at least one memory cell from the plurality of programmable memory cells.
37. The programmable logic integrated circuit of claim 36 wherein the fifth voltage level is used to program the at least one memory cell coupled to the output node.
38. The programmable logic integrated circuit of claim 35 further comprising a plurality of programmable configuration bit memory locations, wherein the output node is coupled to a first programmable configuration bit memory location from the plurality of programmable configuration bit memory locations.
39. The programmable logic integrated circuit of claim 38 wherein the fifth voltage level is used to program the first programmable configuration bit memory location coupled to the output node.
40. The programmable logic integrated circuit of claim 35 further comprising a plurality of logic gates, wherein the output node is coupled to a first logic gate from the plurality of logic gates.
41. The programmable logic integrated circuit of claim 35 wherein the output node is coupled to a second programmable logic integrated circuit.
42. The programmable logic integrated circuit of claim 35 further comprising a plurality of logic array blocks, wherein the output node is coupled to a first logic array block from the plurality of logic array blocks.
43. A programmable logic integrated circuit comprising: a plurality of memory cells, wherein at least one memory cell from the plurality of memory cells is coupled to an output node; and a voltage generator circuit, comprising: a clock generator, generating a first clock signal and a second clock signal operating between a first voltage level and a second voltage level, wherein a rising edge of the second clock occurs when a portion of said first clock signal is a logic high; and a voltage pump, the voltage pump coupled to the first clock signal and the second clock signal, the voltage pump configured to generate a third voltage level at the output node, wherein the third voltage level is above the first voltage level, and the second voltage level.
44. The programmable logic integrated circuit of claim 43 wherein the third voltage level at the output node configures the at least one memory cell coupled to the output node.
45. A programmable logic integrated circuit comprising: a programmable interconnect; a plurality of logic array blocks programmably coupled to the programmable interconnect; and a clock generator, coupled to at least one logic array block from the plurality of logic array blocks, the clock generator generating a first clock signal and a second clock signal operating between a first voltage level and a second voltage level, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal.
46. The programmable logic integrated circuit of claim 45 further comprising a voltage pump coupled to the clock generator, the voltage pump configured to receive the first clock signal and the second clock signal and to generate an output voltage at a third voltage level, wherein the third voltage level is above the first voltage level and the second voltage level.
47. The programmable logic integrated circuit of claim 45 wherein the rising edge of the second clock signal occurs at approximately a center of the pulse width of the first clock signal.
48. The programmable logic integrated circuit of claim 45 wherein the first clock signal is at a logic high for a first portion of a time period of the first clock signal, and the second clock signal is at a logic high for a second portion of a time period of the second clock signal, and wherein the first and second portions are approximately equal.
49. The programmable logic integrated circuit of claim 45 wherein the pulse width of the first clock signal and a pulse width of the second clock signal are approximately equal.
50. The programmable logic integrated circuit of claim 45 wherein frequencies of the first clock signal and the second clock signal are substantially equal.
51. The programmable logic integrated circuit of claim 45 wherein the first voltage level is VDD and the second voltage level is approximately zero volts.
52. An programmable logic integrated circuit comprising: a programmable interconnect; a ring oscillator including a plurality of buffer stages; a ring oscillator output circuit coupled to the ring oscillator, wherein the ring oscillator output circuit receives a first clock signal from a first position of the ring oscillator and a second clock signal from a second position of the ring oscillator, and wherein the ring oscillator output circuit generates a third clock signal and a fourth clock signal overlapping with the third clock signal; a voltage pump, coupled to the third clock signal and the fourth clock signal, the voltage pump configured to generate an output voltage at an output node; and a plurality of logic array blocks programmably coupled to the programmable interconnect, wherein at least one logic array block from the plurality of logic array blocks is coupled to the output node.
53. The programmable logic integrated circuit of claim 52 wherein the ring oscillator includes an odd number of buffer stages.
54. The programmable logic integrated circuit of claim 52 wherein a buffer stage from the plurality of buffer stages of the ring oscillator comprises: a first transistor, coupled between a first voltage supply and a first node, wherein a gate of the first transistor is coupled to a second node; a second transistor coupled between the first node and a second voltage supply, wherein a gate of the second transistor is coupled to the second node; a third transistor coupled between the first node and a third node; and a first capacitor coupled between the third node and the second voltage supply.
55. The programmable logic integrated circuit of claim 54 wherein the first transistor is a PMOS transistor, the second transistor is a NMOS transistor, and the third transistor is a NMOS transistor.
56. The programmable logic integrated circuit of claim 54 wherein the second node is coupled to a previous buffer stage and the third node is coupled to the next buffer stage.
57. The programmable logic integrated circuit of claim 52 wherein the ring oscillator output circuit is coupled to a control signal, wherein the third clock signal and the fourth clock signal are at the same logic level when the control signal is at a first logic level.
58. The programmable logic integrated circuit of claim 52 wherein the voltage pump comprises: a first capacitor coupled to the third clock signal and a first node, wherein the first node is charged by the first capacitor and the third clock signal; and a second capacitor coupled to the fourth clock signal and to a second node, wherein the second node is charged by the second capacitor, the fourth clock signal, and by the charge at the first node, and wherein the charge at the second node generates the output voltage at the output node.
59. The programmable logic integrated circuit of claim 58 wherein the third clock signal and the fourth clock signal operate between a first voltage level and a second voltage level, and wherein the output voltage is at a third voltage level above the first and second voltage levels.
60. The programmable logic integrated circuit of claim 52 wherein the voltage pump comprises: a first capacitor, coupled to a first node and to the third clock signal; a second capacitor, coupled to a second node and to the fourth clock signal; a first transistor, coupled between the first node and a high voltage node, wherein a gate of said first transistor is coupled to the output node; a second transistor, coupled between the high voltage node and the output node, wherein a gate of said second transistor is coupled to the output node; a third transistor, coupled between the first node and the second node, wherein a gate of the third transistor is coupled to the first node; and a fourth transistor, coupled between the second node and the output node, wherein a gate of the fourth transistor is coupled to the second node.
61. The programmable logic integrated circuit of claim 60 wherein the first capacitor and the second capacitor occupy a total area of less than fifty square microns.
62. The programmable logic integrated circuit of claim 60 wherein the first capacitor and the second capacitor are implemented using native transistors.
63. A programmable logic integrated circuit comprising: an oscillator that generates a first clock signal and a second clock signal, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal; a plurality of oscillator buffers coupled to the first clock signal and the second clock signal; a plurality of voltage pumps coupled to the plurality of oscillator buffers, wherein the plurality of voltage pumps are configured to generate high voltage outputs at a plurality of output nodes; and a plurality of logic blocks coupled to the plurality of output nodes.
64. A system for generating voltages on an integrated circuit comprising: a first signal source producing a first clock signal; a second signal source producing a second clock signal, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay not greater than a pulse width of the first clock signal; and a voltage pump, coupled to the first clock signal source and the second clock signal source, wherein the voltage pump comprises: a first capacitor, coupled between a first node and the first signal source; a second capacitor, coupled between a second node and the second signal source; a first transistor coupled between the first node and the second node, having a control electrode coupled to the first node; a second transistor coupled between the second node and an output node, having a control electrode coupled to the second node; a third transistor coupled between a high voltage node and the first node, having a control electrode coupled to the output node.
65. The system of claim 64, wherein the first capacitor and the second capacitor each comprise a transistor.
66. The system of claim 65, wherein the voltage pump further comprises a fourth transistor coupled between the high voltage node and the output node, having a control electrode coupled to the output node.
67. The system of claim 65, wherein the first and second capacitors each comprise a native NMOS device.
68. The system of claim 64, wherein the delay is approximately one half the pulse width of the first clock signal.
69. A method for generating a voltage on an integrated circuit comprising: producing a first clock signal alternating between a first voltage level and a second voltage level; producing a second clock signal alternating between a third voltage level substantially equal to the first voltage level, and a fourth voltage level substantially equal to the second voltage level, wherein a rising edge of the second clock signal follows a rising edge of the first clock signal after a delay, the delay less than a pulse width of the first clock signal, and wherein the first clock signal and second clock signal are generated by a ring oscillator; and inputting the first clock signal and the second clock signal to a voltage pump.
70. The method of claim 69 wherein the first clock signal is generated from a first position of the ring oscillator and the second clock signal is generated from a second position of the ring oscillator, and the first position of the ring oscillator and the second position of the ring oscillator are separated by at least one buffer stage in the ring oscillator.
71. The method of claim 69 wherein the first clock signal is generated from a first position of the ring oscillator and the second clock signal is generated from a second position of the ring oscillator, and the first position of the ring oscillator and the second position of the ring oscillator are separated by at least two buffer stages in the ring oscillator.
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August 10, 1998
May 22, 2001
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