A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits. The condition code logic is also capable of receiving externally computed condition code bits associated with complex instructions and utilizing such condition code bits to produce the output signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor, comprising: execution resources, wherein said execution resources execute a logical instruction by logically combining at least two operands to produce an execution result; and condition code logic that determines less than, greater than, and equal to condition code bits associated with said execution result of said logical instruction concurrently with execution of said logical instruction.
2. The processor of claim 1, wherein: said execution resources execute an arithmetic instruction by arithmetically combining at least two operands to obtain an execution result; and said condition code logic determines less than, greater than, and equal to condition code bits associated with said execution result of said arithmetic instruction concurrently with execution of said arithmetic instruction.
3. The processor of claim 1, said at least two operands including a first operand and a second operand that each include one or more bit positions, each of said one or more bit positions having a bit value, wherein said condition code logic comprises: a single computation stage that receives as inputs individual bit values of bit positions within said first and said second operands, wherein said single computation stage logically combines said individual bit values and outputs one or more logic signals that collectively indicate values for said less than, greater than, and equal to condition code bits.
4. The processor of claim 3, said condition code logic further comprising: at least one merging stage coupled to said computation stage, wherein said at least one merging stage receives as inputs said one or more logic signals and merges said one or more logic signals into at most a greater than signal, a less than signal, and an equal to signal.
5. The processor of claim 4, said execution resources including a complex instruction execution unit that executes complex-type instructions and generates condition code bits associated with each result, wherein said at least one merging stage includes merging logic that receives condition code bits generated by said complex instruction execution unit and utilizes either condition code bits derived from said single computation stage or received from said complex instruction execution unit to generated said greater than signal, less than signal, and equal to signal.
6. The processor of claim 3, each of said at least two operands including at most M bit positions, said single computation stage further comprising: M combination elements that are each associated with a respective one of said M bit positions, each of said M combination elements producing each of a propagate, generate, and kill signal for its respective one of said M bit positions.
7. The processor of claim 6, each of said M combination elements producing said propagate, generate, and kill signals utilizing bit values of at most two bit positions.
8. The processor of claim 6, wherein at least one of said M combination elements computes said propagate, generate, and kill signals in response to a type of said instruction.
9. A method for computing condition code bits in a processor, said method comprising: if a logical instruction is received for execution, executing said logical instruction by logically combining at least two operands to obtain an execution result; and concurrent with execution of said logical instruction, computing less than, greater than, and equal to condition code bits associated with said execution result of said logical instruction.
10. The method of claim 9, and further comprising: if an arithmetic instruction is received for execution, executing said arithmetic instruction by arithmetically combining at least two operands to obtain an execution result; and concurrent with execution of said arithmetic instruction, computing less than, greater than, and equal to condition code bits associated with said execution result of said arithmetic instruction.
11. The method of claim 9, said at least two operands including a first operand and a second operand that each include one or more bit positions, each of said one or more bit positions having a bit value, wherein computing less than, greater than, and equal to bits comprises: receiving as inputs individual bit values of bit positions within said first and said second operands; logically combining said individual bit values; and outputting one or more logic signals that collectively indicate values for said less than, greater than, and equal to condition code bits.
12. The method of claim 11, and further comprising: merging said one or more logic signals into at most a greater than signal, a less than signal, and an equal to signal.
13. The method of claim 12, wherein said processor includes a complex instruction execution unit that executes complex-type instructions, said method further comprising: generating condition code bits associated with each result output by said complex instruction execution unit; and wherein said merging step comprises merging said one or more logic signals into at most a greater than signal, a less than signal, and an equal to signal if a corresponding executed instruction is other than a complex instruction, and otherwise utilizing said condition code bits generated in association with a result output by said complex instruction execution unit to generate said greater than signal, less than signal, and equal to signal.
14. The method of claim 11, each of said at least two operands including at most M bit positions, wherein logically combining said individual bit values comprises: producing each of a propagate, generate, and kill signal for each respective one of said M bit positions.
15. The method of claim 14, wherein producing each of a propagate, generate, and kill signal comprises producing said propagate, generate, and kill signals utilizing bit values of at most two bit positions.
16. The method of claim 14, wherein producing each of a propagate, generate, and kill signal comprises producing, for at least one of said M bit positions, propagate, generate, and kill signals in response to a type of said instruction.
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December 8, 1998
May 22, 2001
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