Self-timing control circuit

1. A self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising: a clock cycle counting circuit for counting oscillation pulses for a period corresponding to a cycle of said master clock and generating a clock cycle count value; and a control clock generating portion for starting a count of the oscillation pulses in synchronized with said master clock, and generating the control clock at a timing when counting up to said clock cycle count value.

2. A self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising: a clock cycle counting circuit for counting oscillation pulses for a period corresponding to a cycle of said mater clock and generating a clock cycle count value; a control clock generating portion for starting a count of the oscillation pulses in synchronized with said master clock, and generating the control clock at a timing when counting up to said clock cycle count value; and wherein said clock cycle counting circuit comprises: a first oscillation circuit for generating said oscillation pulses in a period corresponding to a cycle of said master clock; and a first counter for counting said oscillation pulses generated by said first oscillation circuit.

3. The self-timing control circuit, according to claim 2, wherein said clock cycle counting circuit further comprises a counting clock generating circuit for generating a counting clock, with a pulse width corresponding to the cycle of said master clock, in response to a reset signal; and wherein said first oscillation circuit generates said oscillation pulses in response to said counting clock.

4. The self-timing control circuit, according to any of claims 1 through 3, wherein said control clock generating portion comprises: a second oscillation circuit for starting oscillation in response to said master clock; and a second counter for counting oscillation pulses generated by said second oscillation circuit and generating said control clock, at the timing when counting up to said clock cycle count value.

5. The self-timing control circuit, according to claim 4, wherein said control clock generating portion, said second oscillation circuit stops oscillating and said second counter is reset as timed by said second counter counting up to said clock cycle count value.

6. The self-timing control circuit, according to claim 4, further comprising; a frequency dividing circuit for generating a dividing clock, wherein the frequency of said master clock is multiplied by 1/N (N is an integer of 2 or greater); wherein said control clock generating portion comprises N layers of said second oscillator and second counter; the second oscillator in each layer starts oscillating in response to said dividing clock and a dividing clock with a phase opposite thereto; control clocks generated by the second counter in each layer are synthesized; and a synthesized control clock is generated.

7. The self-timing control circuit, according to any of claims 1 through 3, wherein said clock cycle count value is a count value corresponding to a period of the period of said master clock cycle minus a prescribed dummy delay time; and said prescribed dummy delay time comprises at least a delay time for said master clock at an input buffer.

8. The self-timing control circuit, according to any of claims 1 through 3, wherein the frequency of said oscillation pulses, counted by said clock cycle counting circuit and said control clock generating portion, is switched between a low frequency and high frequency, depending on whether said clock cycle count value is great or small.

9. The self-timing control circuit, according to claim 1, wherein said clock cycle counting circuit comprises a first counter for counting said oscillation pulses during a period corresponding to a cycle of said master clock; said control clock generating portion comprising a oscillation circuit which starts oscillation in response to said master clock, and a second counter which generates said control clock as timed by counting the oscillation pulses generated by said second oscillation circuit and counting up to said clock cycle count value; and the complement of the count value counted by said first counter is set as the initial value for said second counter.

10. A self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising: a clock cycle counting circuit for counting oscillation pulses for a period corresponding to a cycle of said master clock and generating a clock cycle count value; a delay time adjusting circuit for starting a count of oscillation pulses in synchronized with said master clock, and generating an oscillator control signal, according to an adjusting count value at the end of the period corresponding to the cycle of said master clock; and a control clock generating portion for starting a count of the oscillation pulses in synchronized with said master clock, and generating said control clock at a timing when counting up to said clock cycle count value; wherein the frequency of said oscillation pulses, counted by said delay time adjusting circuit and said control clock generating portion, is controlled by said oscillator control signal so that said adjusting count value is matched to said clock cycle count value.

11. The self-timing control circuit, according to claim 10, wherein said clock cycle count value is a count value corresponding to a period of the period of said master clock cycle minus a prescribed dummy delay time; and said prescribed dummy delay time comprises at least a delay time for said master clock at an input buffer.

12. The self-timing control circuit, according to claim 10, wherein said clock cycle count value is a count value corresponding to a period of the period of said master clock cycle minus a prescribed dummy delay time; and said prescribed dummy delay time comprises at least a delay time for said master clock at an input buffer and a delay time at an output buffer which output an output signal in response to said control clock.

13. The self-timing control circuit, according to claim 10, wherein said delay time adjusting circuit comprises a first oscillator for starting oscillation in response to said master clock and a first counter for counting said oscillation pulses generated by said first oscillator; and generates said oscillator control signal depending on the phase of said oscillation pulses at the end of the period corresponding to a cycle of said master clock; wherein the frequency of said first oscillator is controlled by said oscillator control signal.

14. The self-timing control circuit, according to claim 10 or 13, wherein said control clock generating portion comprises: a second oscillator for starting oscillation in response to said master clock; and a second counter for counting said oscillation pulses generated by said second oscillator and generating said control clock at a timing when counting up to said clock cycle count value; wherein the frequency of said second oscillator is controlled by said oscillator control signal.

15. The self-timing control circuit, according to claim 14, wherein said control clock generating portion, said second oscillation circuit stops oscillating and said second counter is reset as timed by said second counter counting up to said clock cycle count value.

16. The self-timing control circuit, according to claim 14, further comprising: a frequency dividing circuit for generating a dividing clock, wherein the frequency of said master clock is multiplied by 1/N (N is an integer of 2 or greater); wherein said control clock generating portion comprises N layers of said second oscillator and second counter; the second oscillator in each layer starts oscillating in response to said dividing clock and a dividing clock with a phase opposite thereto; control clocks generated by the second counter in each layer are synthesized; and a synthesized control clock is generated.

17. The self-timing control circuit, according to claim 10, further comprising: a clock half cycle counting circuit for counting oscillation pulses, for a period corresponding to said master clock cycle, in response to said reset signal and generating a half cycle count value corresponding to half of said master clock cycle; wherein said control clock generating portion further starts a count of the oscillation pulses synchronizing with said master clock and generates a half cycle control clock at a timing of when counting up to said half cycle count value.

18. The self-timing control circuit, according to claim 17, further comprising: a half cycle delay time adjusting circuit for starting a count of the oscillation pulses in synchronized with said master clock, and generating a half cycle oscillator control signal, according to a half cycle adjusting count value at the end of said master clock cycle; wherein the frequency of said oscillation pulses, counted by said half cycle counting circuit and half cycle delay time adjusting circuit, is controlled according to said half cycle oscillator control signal, so that said half cycle adjusting count value is matched to said half cycle count value.

19. The self-timing control circuit, according to claim 10, wherein the frequency of said oscillation pulses, counted by said delay time adjusting circuit and said control clock generating portion, is switched between a low frequency and high frequency, depending on whether said clock cycle count value is great or small.

20. A self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising: a clock cycle counting circuit including a first oscillator for generating oscillation pulses for a period corresponding to said master clock cycle, and a first counter for counting the oscillation pulses generated by said first oscillator and generating a clock cycle count value; and a control clock generating portion including a second oscillator for starting oscillation in response to said master clock, and a second counter for counting the oscillation pulses generated by said second oscillator and generating said control clock at a timing when counting up to said clock cycle count value; wherein the frequency of said first and second oscillators is raised or lowered depending on the presence of an overflow operation of said first counter.

21. The self-timing control circuit, according to claim 20, wherein said first and second oscillators comprise a plurality of oscillators with different frequencies; and said plurality of oscillators is switched among low frequency oscillators and high frequency oscillators depending on the presence of an overflow operation of said first counter.

22. A self-timing control circuit for generating a control clock, synchronized in a prescribed phase relationship to a master clock, comprising: a clock cycle counting circuit including a first oscillator for generating oscillation pulses for a period corresponding to said master clock cycle, in response to a reset signal, and a first counter for counting the oscillation pulses generated by said first oscillator and generating a clock cycle count value; a control clock generating portion including a second oscillator for starting oscillation in response to said master clock, and a second counter for counting the oscillation pulses generated by said second oscillator and generating said control clock at a timing when counting up to said clock cycle count value; and a delay time adjusting circuit including a third oscillator for starting oscillation in response to said master clock and a third counter for counting the oscillation pulses generated by said third oscillator; and generates an oscillator control signal according to the phase of said oscillation pulses at the end of a period corresponding to said master clock cycle; wherein the frequency of said oscillation pulses, counted by said delay time adjusting circuit and said control clock generating portion, is controlled by said oscillator control signal, so that a count value of the third counter at the end is matched to said clock cycle count value; and wherein the frequency of said first and second oscillators is raised or lowered according to the presence of an overflow operation of said first counter.

23. A self-timing control circuit for generating a control clock, synchronized with and having a prescribed phase relationship to a master clock, comprising: a clock cycle count and delay time adjusting circuit comprising a first oscillator for generating oscillation pulses during a period corresponding to a cycle of said master clock in response to a reset signal, and a first counter for counting the oscillation pulses generated by said first oscillator and generating a clock cycle count value, wherein said clock cycle count value is set as the initial value for the first counter, the oscillation pulses generated by said first oscillator is counted by the first counter therefrom so that said clock cycle count and delay time adjusting circuit generates an oscillator control signal at the end of the period corresponding to a cycle of said master clock; and a control clock generating portion comprising a second oscillator which begins oscillation in response to said master clock, and a second counter which generates said control clock as timed by counting the oscillation pulses generated by said second oscillator and counting up to said clock cycle count value, wherein the frequency of said oscillators are controlled by said oscillator control signal so that the count value of the first counter at said ending time matches said clock cycle count value.

24. The self-timing control circuit, according to claim 23, wherein said first counter and second counter are both constituted with down counters or up counters; wherein the complement of the count value of said first counter is set as said initial value to said first and second counters.