A digital image signal is latched by four latches respectively in response to four latch clock signs, which have a frequency that is 1/4 of a frequency of a dot clock signal and phases that are mutually shifted by every period of the dot dock signal. The four latched digital image signals are further latched by a common latch in response to a common latch signal. The digital image signals with respect to four consecutive pixels are then output as one set of digital image signals. The output digital image signals are written into consecutive storage areas in a frame memory, in response to a write sampling dock signal which has a frequency that is 1/4 of the frequency of the dot clock signal The number of latches is regulated according to a frequency of an analog image signal. This arrangement facilitates image processing for high-frequency image signals.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An image processing apparatus, comprising: a first dot dock generation circuit that generates a first dot clock signal, which is synchronous with a first synchronizing signal of a first analog image signal and has a frequency suitable for sampling the first analog image signal; an A-D converter that quantizes the first analog image signal to convert the first analog image signal into digital image signals, and sequentially outputs the digital image signals for respective pixels sampled in synchronism with the first dot dock signal, a series-to-parallel converter having Mw signal hold circuits that sequentially hold the digital image signals with respect to Mw consecutive pixels, the series-to-parallel converter outputting in parallel the digital image signals with respect to Nw consecutive pixels, where Mw is an integer of not less than 2 and Nw is an integer of not less than 1 but not greater than Mw, Nw representing a number of signal hold circuits that are actually used; a first sampling dock generation circuit that generates a first sampling clock signal, which is synchronous with the first synchronizing signal and has a frequency that is 1/Nw of the frequency of the first dot clock signal; a second sampling dock generation circuit that generates Nw second sampling dock signals where Nw corresponds to the number of the signal hold circuits used, the Nw second sampling dock signals having the frequency of the first sampling dock signal and different phases that are mutually shifted by one period of the first dot dock signal and a write control signal regulator that regulates, according to the number Nw of signal hold circuits used, the operation of the first sampling clock generation circuit and the second sampling dock generation circuit and supplies the Nw second sampling clock signs to the Nw signal hold circuits, so as to cause the digital image signals with respect to the Nw consecutive pixels to be output from the series-to-parallel converter as one set of digital image signals.
2. An image processing apparatus in accordance with claim 1, further comprising: a selective control circuit that suspends operation of (Mw-Nw) signal hold circuits which are not used, wherein the write control signal regulator controls the selective control circuit according to the number Nw.
3. An image processing apparatus in accordance with claim 2, further comprising: a number determination circuit that determines the number Nw of the signal hold circuits used according to the frequency of the first dot clock signal.
4. An image processing apparatus in accordance with claim 1, wherein the Nw second sampling clock signals having the mutually shifted phases are output together with the one set of digital image signals from the image processing apparatus.
5. An image processing apparatus in accordance with claim 1, wherein the second sampling clock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases, in response to the first sampling clock signal and the first dot clok signal.
6. An image processing apparatus in accordance with claim 1, wherein the second sampling clock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases by successively delaying the first sampling clock signal.
7. An image processing apparatus in accordance with claim 1, wherein the first sampling clock generation circuit further generates a 90-degree phase shift clock signal having a phase difference of 90 degrees from the first sampling clock signal and the second sampling clock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases, in response to the first sampling clock signal and the 90-degree phase shift clock signal.
8. An image processing apparatus in accordance with claim 1, wherein the second sampling clock generation circuit initializes the Nw second sampling clock signals having the mutually shifted phases, in response to the pulse of the first synchronizing signal, so that the first synchronizing signal and each of the Nw second sampling clock signals having the mutually shifted phases has a predetermined phase relation.
9. An image processing apparatus in accordance with claim 1, further comprising: a third sampling clock generation circuit that generates a third sampling clock signal having a phase suitable for sampling the one set of digital image signals, the third sampling dock signal being output from the image processing apparatus together with the one set of digital image signals.
10. An image processing apparatus in accordance with claim 1, further comprising: a fourth sampling clock generation circuit that generates a fourth sampling clock signal, which is synchronous with the first synchronizing signal and has a frequency that is Nx times the frequency of the first dot clock signal, where Nx is an integer of not less than 2, wherein the A-D converter comprises a .DELTA..SIGMA. modulation circuit and a digital filter, and quantizes the first analog image signal in response to the fourth sampling clock signal and sequentially outputs the digital image signals of the respective pixels sampled synchronously with the first dot clock signal.
11. An image processing apparatus in accordance with claim 1, wherein the first analog signal includes a plurality of color component signals, and wherein the A-D converter includes a plurality of A-D converter elements for the respective color component signals, and the series-to-parallel converter includes a plurality of converter elements for the respective color component signals.
12. An image processing apparatus in accordance with claim 1, wherein the series-to-parallel converter comprises: multiple-stage digital image signal phase regulation circuits to output the Nw digital image signals at an identical phase, wherein the multiple-stage digital image signal phase regulation circuits have a hierarchical structure, where the number of circuits included in each stage gradually decreases towards a last stage, each of plural digital image signal phase regulation circuits included in each stage except the last stage holds a plurality of input digital image signals at a predetermined phase, which is different from the phases of the other digital image signal phase regulation circuits induced in the same stage and supplies the digital image signals of the predetermined phase to a digital image signal phase regulation circuit included in a next stage, and the digital image signal phase regulation circuits included in the last stage holds the Nw digital image signals at an identical phase, which are supplied from a preceding stage.
13. An image processing apparatus in accordance with claim 1, further comprising: an image memory that stores digital image signals; and a write controller that writes the digital image signals with respect to the Nw consecutive pixels into a consecutive storage area in the image memory.
14. An image processing apparatus in accordance with claim 13, wherein the write controller comprises: multiple-stage digital image signal phase regulation circuits to output the Nw digital image signals, which are output in parallel from the series-to-parallel converter, at an identical phase, wherein the multiple-stage digital image signal phase regulation circuits have a hierarchical structure, where the number of circuits included in each stage gradually decreases towards a last stage, each of plural digital image signal phase regulation circuits included in each stage except the last stage holds a plurality of input digital image signals at a predetermined phase, which is different from the phases of the other digital image signal phase regulation circuits included in the same stage and supplies the digital image signals of the predetermined phase to a digital image signal phase regulation circuit included in a next stage, and the digital image signal phase regulation circuits included in the last stage holds the Nw digital image signals at an identical phase, which are supplied from a preceding stage.
15. An image processing apparatus in accordance with claim 13, further comprising: Mr D-A converters, where Mr is an integer of not less than 2; a second dot clock generation circuit that generates a second dot clock signal having a frequency suitable for sampling a second analog image signal-to-be-output; a fifth sampling dock generation circuit that generates a fifth sampling clock signal, which has a frequency that is IINr the frequency of the second dot dock signal, where Nr is an integer of not less than 1 but not greater than Mr and represents a number of D-A converters that are actual used, the fifth sampling clock signal being synchronous with a second synchronizing signal of the second analog image signal; a sixth sampling dock generation circuit that generates Nr sixth sampling clock signals based on the second dot clock signal, the sixth sampling dock signals having the frequency of the fifth sampling clock signal and different phases that are mutually shifted by one period of the second dot clock signal; a read controller that reads digital image signals with respect to Nr consecutive pixels from the image memory in synchronism with the fifth sampling clock signal; a D-A conversion selective control circuit that suspends operation of Mr-Nr) unused D-A converters according to the number Nr; a read control signal regulator that determines the number Nr of the D-A converters used according to the frequency of the second dot clock signal to control the D-A conversion selective control circuit, regulates operation of the fifth sampling clock generation circuit and the sixth sampling clock generation circuit according to the number Nr, and causes the digital image signals with respect to the Nr consecutive pixels to be successively subjected to D-A conversion by the Nr D-A converters according to the Nr fifth sampling clock signals, so as to generate Nr partial analog image signals having different phases; and a video switch that sequentially switches the Nr partial analog image signals output from the Nr D-A converters synchronously with the second dot clock signal, so as to generate the second analog image signal.
16. An integrated circuit, comprising: a first dot clock generation circuit that generates a first dot clock signal, which is synchronous with a first synchronizing signal of a first analog image signal and has a frequency suitable for sampling the first analog image signal; an A-D converter that quantizes the first analog image signal to convert the first analog image signal into digital image signals, and sequentially outputs the digital image signals for respective pixels sampled in synchronism with the first dot clock signal; a series-to-parallel converter having Mw signal hold circuits that sequentially hold the digital image signals with respect to Mw consecutive pixels, the series-to-parallel converter outputting in parallel the digital image signals with respect to Nw consecutive pixels, where Mw is an integer of not less than 2 and Nw is an integer of not less than 1 but not greater than Mw, Nw representing a number of signal hold circuits that are actually used; a first sampling clock generation circuit that generates a first sampling clock signal, which is synchronous with the first synchronizing signal and has a frequency that is 1/Nw of the frequency of the first dot clock signal; a second sampling clock generation circuit that generates Nw second sampling clock signals where Nw corresponds to the number of the signal hold circuits used, which is set based on the frequency of the first dot clock signal, wherein the Nw second sampling clock signals have the frequency of the first sampling clock signal and different phases that are mutually shifted by one period of the first dot clock signal, wherein the operation of the f sampling clock generation circuit and the second sampling clock generation circuit is regulated according to the number Nw of the signal hold circuits used, and the Nw second sampling clock signals are supplied to the Nw signal hold circuits, so that the digital image signals with respect to the Nw consecutive pixels are output from the series-to-parallel converter as one set of digital image signals.
17. An integrated circuit in accordance with claim 16, further comprising: a selective control circuit that suspends operation of (Mw-Nw) signal hold circuits which are not used, wherein operation of the selective control circuit is controlled according to the number Nw of the signal hold circuits used.
18. An integrated circuit in accordance with claim 16, wherein the Nw second sampling clock signals having the mutually shifted phases are output together with the one set of digital image signals from the integrated circuit.
19. An integrated circuit in accordance with claim 16, wherein the second sampling clock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases, in response to the first sampling clock signal and the first dot clock signal.
20. An integrated circuit in accordance with claim 16, wherein the second sampling dock generation circuit generates the Nw second sampling clock signals having the mutually shifted phases by successively delaying the first sampling clock signal.
21. An integrated circuit in accordance with 16, wherein the first sampling clock generation circuit further generates a 90-degree phase shit clock signal having a phase difference of 90 degrees from the first sampling clock signal and the second sampling clock generation circuit generates the Nw second sampling dock signals having the mutually shifted phases, in response to the first sampling clock signal and the 90 degree phase sift clock signal.
22. An integrated circuit in accordance with claim 16, wherein the second sampling clock generation circuit initializes the Nw second sampling clock signals having the mutually shifted phases, in response to the pulse of the first synchronizing signal, so that the first synchronizing signal and each of the Nw second sampling dock signals having the mutually shifted phases has a predetermined phase relation.
23. An integrated circuit in accordance with claim 16, further comprising: a third sampling clock generation circuit that generates a third sampling clock signal having a phase suitable for sampling the one set of digital image signals, the third sampling clock signal being output from the image processing apparatus together with the one set of digital image signals.
24. An integrated circuit in accordance with claim 16, further comprising: a fourth sampling clock generation circuit that generates a fourth sampling clock signal which is synchronous with the ft synchronizing signal and has a frequency that is Nx times the frequency of the first dot clock signal, where Nx is an integer of not less than 2, wherein the A-D converter comprises a .DELTA..SIGMA. modulation circuit and a digital filter, and quantizes the first analog image signal in response to the fourth sampling clock signal and sequentially outputs the digital image signals of the respective pixels sampled synchronously with the first dot clock signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 26, 1999
May 29, 2001
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