One embodiment of the invention is a method for forming a raised structure on a semiconductor wafer. In the method, a patterned masking layer is formed over a wafer layer. The patterned masking layer typically includes a first mask covering a first region of the wafer layer and at least one side mask adjacent to the first mask, covering a side region of the wafer layer. After forming the patterned masking layer, exposed portions of the wafer layer adjacent the masks are removed using the patterned masking layer. This leaves a first raised structure (relative to an adjacent removed area) in the first substrate region and a sacrificial raised structure in the side region adjacent the first raised structure. After removing the exposed portions of the wafer layer, the sacrificial raised structure is selectively removed while leaving the first raised structure intact. The sacrificial raised structure and overlying side mask typically reduce the area of the wafer layer which would otherwise be exposed during the removal. This facilitates the formation of the vertical sidewall on the raised structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a structure having a vertical sidewall on a wafer layers comprising: forming a patterned masking layer over the wafer layer, the patterned masking layer including a first mask covering a first region of the wafer layer and at least one side mask adjacent the first mask and covering a side region of the wafer layer; removing uncovered portions of the wafer layer using the patterned masking layer to leave a first raised structure in the first region of the wafer layer and a sacrificial raised structure in the side region of the wafer layer adjacent the first raised structure; and after removing the uncovered portions of the wafer layer, selectively removing the sacrificial raised structure while leaving the first raised structure intact.
2. The method of claim 1, wherein forming the patterned masking layer includes forming an opening between the first mask and the side mask having a width of 40 microns or less.
3. The method of claim 2, wherein forming the opening includes forming the opening width with a dimension of 20 microns.
4. The method of claim 2, wherein removing uncovered portions of the wafer layer to leave the first raised structure includes forming a gap having a width of 40 microns or less between the first raised structure and the sacrificial raised structure.
5. The method of claim 2, wherein removing uncovered portions of the wafer layer includes leaving the first raised structure with a sidewall having a verticality of at least 90.degree..+-.0.6.degree..
6. The method of claim 1, wherein forming the patterned masking layer includes forming and patterning a composite layer of the same photoresist material over the wafer layer and patterning the composite layer.
7. The method of claim 6, wherein forming and patterning the composite layer of the same photoresist material includes: depositing and heating a first layer of the photoresist material; depositing a second layer of the photoresist material over the first layer, after heating the first layer, to form a double layer of the photoresist material and heating the double layer of the photoresist material; and patterning the double layer of the photoresist material.
8. The method of claim 7, wherein etching the wafer layer includes forming a trench having a depth of 60 microns or more between the first raised structure and each of the sacrificial raised structure.
9. The method of claim 8, wherein removing uncovered portions of the wafer layer includes forming the first raised structure with a surface roughness of 30 nm rms or less.
10. The method of claim 9, wherein the wafer layer is a layer of a substrate disposed over an insulating layer, wherein removing the uncovered portions of the wafer layer includes removing exposed wafer layer regions surrounding the side region of the wafer layer to leave the sacrificial raised structure on the insulating layer isolated from the first raised structures and selectively removing the sacrificial raised structure includes removing the insulating layer from beneath the sacrificial raised structure, thereby freeing the sacrificial raised structure from the wafer layer.
11. The method of claim 10, wherein selectively removing the sacrificial raised structures includes dipping the wafer layer in an etching solution, wherein the sacrificial raised feature falls into the etching solution.
12. The method of claim 1, wherein forming the patterned masking layer includes forming openings in the patterned masking layer exposing wafer layer regions surrounding the side region.
13. The method of claim 1, wherein selectively removing the sacrificial raised structure includes forming a masking layer selectively masking the first raised structure and removing the sacrificial raised structure using the masking layer.
14. The method of claim 13, wherein removing the sacrificial raised structure using the masking layer includes etching the sacrificial raised structure using the masking layer to keep the first raised structure intact.
15. The method of claim 1, wherein the wafer layer is a layer of a substrate disposed over an insulating layer, wherein removing the uncovered portions of the wafer layer includes removing exposed wafer layer regions surrounding the side region of the wafer layer to leave the sacrificial raised structure on the insulating layer isolated from the first raised structure, and selectively removing the sacrificial raised structure includes removing the insulating layer from beneath the sacrificial raised structure, thereby freeing the sacrificial raised structure from the wafer layer.
16. The method of claim 15, wherein selectively removing the sacrificial raised structures includes dipping the wafer layer in an etching solution, wherein the sacrificial raised feature falls into the etching solution.
17. The method of claim 1, wherein removing uncovered portions of the wafer layer includes leaving the first raised structure with a sidewall having a verticality of at least 90.degree..+-.0.6.degree..
18. A method of forming a structure having a vertical sidewall on a wafer layer, comprising: forming a patterned masking layer over the wafer layer, the patterned masking layer including a first mask covering a first region of the wafer layer and at least one side mask adjacent the first mask and covering a side region of the wafer layer; removing uncovered portions of the wafer layer using the patterned masking layer to leave a first raised structure in the first region of the wafer layer and a sacrificial raised structure in the side region of the wafer layer adjacent the first raised structure, the sacrificial raised structure being isolated from the first raised structure; and after removing the uncovered portions of the wafer layer, selectively removing the sacrificial raised structure while leaving the first raised structure intact.
19. The method of claim 18, wherein the wafer layer is a layer of a substrate disposed over an insulating layer, wherein removing the uncovered portions of the wafer layer includes removing exposed wafer layer regions surrounding the side region of the wafer layer to leave the sacrificial raised structure on the insulating layer isolated from the first raised structure, and selectively removing the sacrificial raised structure includes removing the insulating layer from beneath the sacrificial raised structure, thereby freeing the sacrificial raised structure from the wafer layer.
20. The method of claim 19, wherein selectively removing the sacrificial raised structures includes dipping the wafer layer in an etching solution, wherein the sacrificial raised feature falls into the etching solution.
21. The method of claim 18, wherein forming the patterned masking layer includes forming a composite layer of the same photoresist material over the wafer layer.
22. The method of claim 18, wherein removing uncovered portions of the wafer layer includes leaving the first raised structure with a sidewall having a verticality of at least 90.degree..+-.0.6.degree..
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 11, 1999
June 5, 2001
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