A method of forming a contact for a dynamic random access memory device is disclosed. In this method, a first insulating layer is formed on a semiconductor substrate. First and second contact pads are formed in the first insulating layer and on a semiconductor substrate in such a manner that a top surface of the first insulating layer is higher than top surfaces of the contact pads. Then a second insulating layer is formed over the substrate, which layer shows a bad step coverage. The second insulating layer is etched until the surfaces of the first and second contact pads are exposed. Then a first conductive layer is formed over the entire surface of the semiconductor substrate, and the first conductive layer is flattened, leaving some thickness of the second insulating layer. Then a second conductive layer is formed over the first conductive layer, and the second and first conductive layers are sequentially etched using a bit line forming mask, to form a bit line. Under this condition, the first conductive layer on the first contact pad is over-etched to form an electrical insulation from the bit line. When forming the direct contacts of a cell region and a core region, the photo process for forming the DC of the cell region or the BC and DC of the cell region, and the photo process for forming the DC of the core region can be skipped to simplify the formation process, thereby saving manufacturing costs.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a contact in a semiconductor memory device, comprising: forming a transistor over a semiconductor substrate; forming a first insulating layer over the semiconductor substrate; forming first and second contact pads in the insulating layer, top surfaces of the contact pads being lower in level as compared to a top surface of the first insulating layer; forming a second insulating layer over the first insulating layer, the second insulating layer exhibiting a poor step coverage; etching the second insulating layer until surfaces of the first and second contact pads are exposed; forming a first conductive layer over the semiconductor substrate and the first and second insulating layers; forming a second conductive layer over the first conductive layer.
2. A method of forming a contact in a semiconductor memory device, as recited in claim 1, further comprising flattening the first conductive layer to leave a partial thickness thereof over the second insulating layer.
3. A method of forming a contact in a semiconductor memory device, as recited in claim 1, further comprising removing a partial thickness of the second and first insulating layers along both sides of the bit line through an etch-back process using the bit line as a mask.
4. A method of forming a contact in a semiconductor memory device, as recited in claim 1, wherein the first insulating layer is an oxide layer, and the second insulating layer comprises a material selected from the group consisting of SiON, PE-SiN, PE-SiH.sub.4, and plasma enhanced-tetraethylortho-silicate (PE-TEOS).
5. A method of forming a contact in a semiconductor memory device, as recited in claim 1, wherein the first self-aligned contact pad is a storage node contact pad, and the second self-aligned contact pad is a bit line contact pad.
6. A method of forming a contact in a semiconductor memory device, as recited in claim 1, wherein the first conductive layer comprises polysilicon, and the second conductive layer comprises tungsten silicide.
7. A method of forming a contact in a semiconductor memory device, as recited in claim 1, wherein the partial thickness of the second insulating layer is about 70 nm and the diameter of the contact pads is about 260 nm.
8. A method of forming a contact in a semiconductor memory device, comprising: forming a transistor over a semiconductor substrate; forming a first insulating layer over the semiconductor substrate; forming first and second contact pads in the insulating layer, top surfaces of the contact pads being lower in level as compared to a top surface of the first insulating layer; forming a second insulating layer over the first insulating layer, the second insulating layer exhibiting a poor step coverage; etching the second insulating layer until surfaces of the first and second contact pads are exposed; forming a first conductive layer over the semiconductor substrate and the first and second insulating layers; forming a second conductive layer over the first conductive layer; and sequentially etching the second and first conductive layers by using a bit line forming mask to form a bit line that is electrically connected to the contact pads, wherein the first conductive layer over the first self-aligned contact pad is over-etched to electrically insulate the first contact pad from the bit line.
9. A method of forming a contact in a semiconductor memory device, as recited in claim 8, further comprising etching the first and second insulating layers in the core region, using a contact hole forming mask, to form a direct contact hole.
10. A method for forming a contact in a semiconductor memory device, comprising: forming a transistor over a semiconductor substrate having a cell array region and a core region; forming a first insulating layer over the semiconductor substrate; etching the first insulating layer until a surface of the semiconductor substrate is exposed, to form a first and second contact holes in the cell array region and a third contact hole in the core region; filling the contact holes with a first conductive layer; etching the first conductive layer to form first and second self-aligned contact pads in the cell array region and a third self-aligned contact pad in the core region, the first, second, and third contact pads being recessed in the contact holes a depth from a top surface of the first insulating layer; and forming a second insulating layer over the first insulating layer, the second insulating layer exhibiting a poor step coverage, and exposing upper surfaces of the first, second, and third contact pads.
11. A method for forming a contact in a semiconductor memory device, as recited in claim 10, wherein the first self-aligned contact pad is formed in the cell array region and the second self-aligned contact pad is formed in the core region.
12. A method for forming a contact in a semiconductor memory device, as recited in claim 10, further comprising removing a partial thickness of the first and second insulating layers at both sides of the bit line, using the bit line as a mask, after forming the bit line.
13. A method for forming a contact in a semiconductor memory device, as recited in claim 10, wherein the first insulating layer comprises an oxide, and the second insulating layer comprise a material selected from the group consisting of SiON, PE-SiN, PE-SiH.sub.4 and PE-TEOS (plasma enhanced-tetraethylortho-silicate).
14. A method for forming a contact in a semiconductor memory device, as recited in claim 10, wherein the first and second conductive layers comprise polysilicon, and the third conductive layer comprises tungsten silicide.
15. A method for forming a contact in a semiconductor memory device, as recited in claim 10, wherein the first self-aligned contact pad is a storage node contact pad, and the second and third self-aligned contact pads are bit line contact pads.
16. A method for forming a contact in a semiconductor memory device, comprising; forming a transistor over a semiconductor substrate having a cell array region and a core region; forming a first insulating layer over the semiconductor substrate; etching the first insulating layer until a surface of the semiconductor substrate is exposed, to form a first and second contact holes in the cell array region and a third contact hole in the core region; filling the contact holes with a first conductive layer; etching the first conductive layer to form first and second self-aligned contact pads in the cell array region and a third self-aligned contact pad in the core region, the first, second, and third contact pads being recessed in the contact holes a depth from a top surface of the first insulating layer; forming a second insulating layer over the first insulating layer, the second insulating layer exhibiting a poor step coverage, and exposing upper surfaces of the first, second, and third contact pads, forming second and third conductive layers over the semiconductor substrate and the first, second, and third contact pads; and etching the second and third conductive layers using a bit line forming mask so as to form a bit line, wherein the second conductive layer over the first contact pad is over-etched to electrically insulate the first contact pad from the bit line.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 16, 1999
July 3, 2001
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