In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method to produce an EEPROM for mass storage, comprising: a) forming a plurality of polysilicon floating gates with associated sidewall spacers with a dielectric layer thereon upon an oxide layer on a semiconductor substrate above a plurality of wells implanted therein, b) ion implanting a plurality of drain and plurality of source regions in said wells using said floating gates with the sidewall spacers as a mask, c) double diffusing said source regions with sidewall spacers adjacent to source region removed, d) forming isolation oxidation, removing sidewall spacers adjacent to said drain regions and growing an interpoly dielectric, e) depositing a layer of polysilicon and forming a plurality of control gates over a plurality of said floating gates.
2. The method of claim 1 wherein, forming a thick floating gate provides a size of said sidewall spacer necessary to produce an offset for a select transistor channel.
3. The method of claim 1 wherein, removing said sidewall spacers adjacent to said drain regions after said isolation oxidation retards oxidation on sides of said floating gates.
4. The method of claim 1 wherein, forming said plurality of control gates over a plurality of floating gates produces a plurality of word lines of a memory.
5. The method of claim 1 wherein, growing said interpoly dielectric provides a uniform field enhanced tunneling injector along edges of said floating gates to minimize endurance induced degradation caused by repeated erasing and reading of charge on said floating gate.
6. The method of claim 1 wherein, forming said floating gates with a thick dielectric is done to minimize floating gate to control gate coupling and allows a high field to be developed along an edge of said floating gate during programming to permit fast charge transfer.
7. The method of claim 1 wherein, double diffusing said source regions and removing said sidewall spacers adjacent to source region is done with a shared masking step.
8. A method to produce an electrically erasable and programmable (EEPROM) for mass storage applications, comprising: a) forming a well in a semiconductor substrate, b) implanting ions into said well to establish a threshold voltage, c) forming a gate isolation layer on top of said substrate, d) forming a floating gate structure comprising a first layer of polysilicon with a dielectric insulator thereupon, e) forming sidewall spacers on sides of said floating gate structure, f) ion implanting a plurality of drain and source regions in said well using said sidewall spacers as a mask, g) removing sidewalls adjacent to said source regions, h) double diffusing said source regions, i) implanting a source within said source region, j) depositing an isolation oxidation on source and drain regions and removing side wall spacers, k) growing an interpoly dielectric, l) depositing a second layer of polysilicon, k) forming a control gate structure from said second layer of polysilicon and covering a plurality of said floating gate structures.
9. The method of claim 8 wherein, forming a thick floating gate structure provides a size of said sidewall spacer necessary to produce an offset for a select transistor channel.
10. The method of claim 8 wherein, removing said sidewall spacers adjacent to said drain regions after said isolation oxidation retards oxidation on sides of said floating gates.
11. The method of claim 8 wherein, forming said plurality of control gates over a plurality of floating gates produces a plurality of word lines of a memory.
12. The method of claim 8 wherein, growing said interpoly dielectric provides a uniform field enhanced tunneling injector along edges of said floating gates to minimize endurance induced degradation caused by repeated erasing and reading of charge on said floating gate.
13. The method of claim 8 wherein, forming said floating gate structure with a thick dielectric is done to minimize floating gate to control gate coupling and allows a high field to be developed along an edge of said floating gate during programming to permit fast charge transfer.
14. The method of claim 8 wherein, double diffusing said source regions and removing said sidewall spacers adjacent to the source region is done with a shared masking step.
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January 19, 2000
July 10, 2001
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