A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of generating a clock phase signal comprising the acts of: providing a first delay line having a plurality of first delay elements; driving said first delay line with a clock signal having a period; counting said first delay elements needed to provide a delay approximately equal to said period; providing a second delay line having a plurality of second delay element, said second delay elements having a delay equal to a fraction of said first delay elements; inputting said clock signal to said second delay line; and counting said second delay elements during said period to produce a clock phase signal having a fixed phase in relationship to said clock signal, wherein said phase is equal to said fraction.
2. The method of claim 1, further comprising the acts of: coupling said first delay line to a shift register; and coupling said shift register to a counter.
3. The method of claim 2, wherein said counting said first delay elements comprises: providing an additional signal to said first delay line, whereby said first delay elements receive said additional signal sequentially; latching output signals of said first delay elements into said shift register for said period; and shifting said output signals in said shift register into said counter.
4. The method of claim 1, further comprising the act of: providing a multiplexer to count said second delay elements.
5. The method of claim 4, further comprising the acts of: coupling said first delay line to a shift register; coupling said shift register to a counter to count said first delay elements; and connecting said multiplexer element to receive a count from said counter.
6. The method of claim 1, further comprising the acts of: providing a third delay line having a plurality of third delay elements, wherein said third delay elements have a delay equal to a second fraction of said period; inputting said clock signal to said third delay line; and counting said third delay elements during said period to produce a second clock phase signal having a fixed second phase in relationship to said clock signal, wherein said second phase is equal to said second fraction.
7. The method of claim 1, further comprising the act of: generating a control signal for operating a DRAM array from said clock phase signal.
8. A method for generating a timing signal from a clock signal comprising the acts of: providing a plurality of first delay stages; counting said first delay stages equal to a period of said clock signal; providing a plurality of second delay stages having a delay equal to a fraction of a delay of said first delay stages; and counting said second delay stages during said period to produce said timing signal, wherein said timing signal is equal to said fraction of said period.
9. The method of claim 8, wherein said counting said first delay stages comprises: providing a first delay line having a plurality of first delay elements, said first delay elements providing said first delay stages; driving said first delay line with said clock signal; providing an additional signal to said first delay line, whereby said first delay elements are signaled sequentially with said additional signal; latching output signals of said first delay elements into a shift register for said period; and shifting said output signals into a counter, thereby to count said first delay elements.
10. The method of claim 8, wherein said second delay stages comprise second delay elements of a second delay line, and wherein said counting said second delay stages comprises: connecting a multiplexer to said second delay line; inputting said count to said multiplexer; and driving said second delay line with said clock signal; wherein said multiplexer receives a count of said second delay elements during said period of said clock signal to produce said timing signal.
11. The method of claim 8, further comprising the act of: generating a control signal for operating a DRAM array from said timing signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 7, 2000
July 10, 2001
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