A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A direct memory access engine for supporting multiple virtual direct memory access channels, comprising: a direct memory access controller, comprising: a physical direct memory access control block; a physical direct memory access channel resource; a physical direct memory access channel coupled to the physical direct memory access control block and the physical direct memory access channel resource; a plurality of virtual direct memory access channels coupled to the physical direct memory access control block and sharing the physical direct memory access channel, the physical direct memory access control block, and the physical direct memory access channel resource; and a memory including a parameter table storing parameters for the plurality of virtual direct memory access channels.
2. The direct memory access engine of claim 1, wherein an execution unit loads parameters for an active virtual direct memory access channel of the plurality of virtual direct memory access channels from the parameter table to the physical direct memory access channel resource and the physical direct memory access control block.
3. The direct memory access engine of claim 1, wherein one channel of the plurality of virtual direct memory access channels is active at a given time.
4. The direct memory access engine of claim 1, wherein the physical direct memory access resource and the physical direct memory access control block store parameters for an active virtual direct memory access channel of the plurality of virtual direct memory access channels.
5. The direct memory access engine of claim 1, wherein the direct memory access controller performs a direct memory access transfer for an active virtual direct memory access channel of the plurality of virtual direct memory access channels over the physical direct memory access channel based on the parameters.
6. The direct memory access engine of claim 1, comprising: a direct memory access request line for an active channel of the plurality of virtual direct memory access channels.
7. The direct memory access engine of claim 1, comprising: a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.
8. A microcontroller for supporting multiple virtual direct memory access channels, comprising: an execution unit; a direct memory access unit coupled to the execution unit, comprising: a direct memory access engine, comprising: a physical direct memory access control block; a physical direct memory access channel resource; a physical direct memory access channel coupled to the physical direct memory access control block and the physical direct memory access channel resource; a plurality of virtual direct memory access channels coupled to the physical direct memory access control block and sharing the physical direct memory access control block and the physical direct memory access channel resource; and a memory including a parameter table storing parameters for the plurality of virtual direct memory access channels.
9. The direct memory access engine of claim 7, wherein an execution unit loads parameters for an active virtual direct memory access channel of the plurality of virtual direct memory access channels from the parameter table to the physical direct memory access channel resource and the physical direct memory access control block.
10. The microcontroller of claim 8, wherein one channel of the plurality of virtual direct memory access channels is active at a given time.
11. The microcontroller of claim 8, wherein the physical direct memory access channel resource and the physical direct memory access control block store parameters for an active virtual direct memory access channel of the plurality of virtual direct memory access channels.
12. The microcontroller of claim 8, wherein the direct memory access controller performs a direct memory access transfer for an active virtual direct memory access channel of the plurality of virtual direct memory access channels over the physical direct memory access channel based on the parameters.
13. The microcontroller of claim 8, the direct memory access engine comprising: a direct memory access request line for an active channel of the plurality of virtual direct memory access channels.
14. The microcontroller of claim 8, the direct memory access engine comprising: a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.
15. The microcontroller of claim 8, the direct memory access engine including a direct memory access request line for an active channel of the plurality of virtual direct memory access channels and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels, further comprising: a direct memory access request/acknowledge port block coupled to the direct memory access engine for receiving the direct memory access request line and providing the direct memory access acknowledge line.
16. The microcontroller of claim 15, the direct memory access request/acknowledge port block comprising: steering logic for directing a direct memory access acknowledge signal corresponding to the active virtual direct memory access channel from the direct memory access controller to the direct memory access acknowledge line.
17. The microcontroller of claim 15, further comprising: a device coupled to the direct memory access request/acknowledge port block for providing a direct memory access acknowledge signal to the direct memory access request acknowledge port block and receiving a direct memory access acknowledge signal from the direct memory access request/acknowledge port block.
18. A method of controlling a direct memory access transfer using a direct memory access controller engine for supporting multiple virtual direct memory access channels, the direct memory access engine including a direct memory access controller having a physical direct memory access control block, a physical direct memory access channel resource, a physical direct memory access channel, and a plurality of virtual direct memory access channels, the plurality of virtual direct memory access channels sharing the physical direct memory access channel, the physical direct memory access control block, and the physical direct memory access channel resource, the direct memory access controller engine further including a memory having a parameter table for storing parameters for the plurality of virtual direct memory access channels, the method comprising the steps of: loading the direct memory access controller with parameters from the parameter table for a first active virtual direct memory access channel of the plurality of virtual direct memory access channels; and performing a direct memory access transfer for the first active virtual direct memory access channel over the physical direct memory access channel based on the parameters loaded to the direct memory access controller.
19. The method of claim 18, further comprising the step of: loading the direct memory access controller with parameters from the parameter table for a second active virtual direct memory access channel of the plurality of virtual direct memory access channels; and performing a direct memory access transfer for the second active virtual direct memory access channel over the physical direct memory access channel based on the parameters loaded to the direct memory access controller.
20. The method of claim 18, wherein the loading step is performed by an execution unit.
21. The method of claim 18, wherein the step of performing a direct memory access transfer is controlled by the direct memory access control block.
22. The method of claim 18, further comprising the step of: providing the direct memory access engine in a microcontroller.
23. The method of claim 18, the loading step comprising the step of: loading a portion of the parameters to the physical direct memory access channel resource.
24. The method of claim 18, the loading step comprising the step of: loading a portion of the parameters to the physical direct memory access control block.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 24, 1998
July 10, 2001
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