Semiconductor memory device which operates in synchronism with a clock signal

1. A semiconductor memory device having a data path divided into a plurality of stages, each having a pipeline structure and designed to operate in synchronism with a clock signal, said device comprising: a signal generating circuit for generating a first signal representing a first latency and a second signal representing a second latency smaller than the first latency in response to a command; a buffer circuit having an input terminal and an output terminal, for receiving a clock signal at the input terminal and outputting the clock signal from an output terminal; a first transfer gate connected to the output terminal of the buffer circuit, for outputting the clock signal supplied from the buffer circuit as an internal clock signal in response to the first signal supplied from the signal generating circuit; a delay circuit connected to the output terminal of the buffer circuit, for delaying the clock signal supplied from the buffer circuit; and a second transfer gate connected to an output terminal of the buffer circuit, for outputting the clock signal supplied from the delay circuit as the internal clock signal in response to the second signal supplied from the signal generating circuit, wherein said delay circuit has a delay time equal to the difference between a cycle time of the first latency and a cycle time of the second latency.

2. A semiconductor memory device having a data path divided into first, second and third stages, each having a pipeline structure and designed to operate in synchronism with a clock signal, said device comprising: a signal generating circuit for generating, in response to a command, a first signal representing a first latency and a second signal representing a second latency smaller than the first latency; a first buffer circuit for receiving a clock signal and outputting the clock signal; a gate circuit connected to an output terminal of the first buffer circuit, for outputting the clock signal supplied from the first buffer circuit as a first clock signal in response to a command; a second buffer circuit for receiving the clock signal and outputting the clock signal; a first transfer gate connected to an output terminal of the second buffer circuit, for outputting the clock signal supplied from the second buffer circuit as a second clock signal in response to the first signal supplied from the signal generating circuit; a delay circuit connected to the output terminal of the second buffer circuit, for delaying the clock signal supplied from the second buffer circuit; and a second transfer gate connected to an output terminal of the delay circuit, for outputting the clock signal supplied from the delay circuit as the second clock signal in response to the second signal supplied from the signal generating circuit, wherein said delay circuit has a delay time corresponding to the difference between a cycle time of the first latency and a cycle time of the second latency.

3. A device according to claim 2, further comprising a transfer gate connected to the gate circuit, for controlling a timing of transferring an address signal in accordance with the first clock signal.

4. A device according to claim 2, further comprising a logic circuit for receiving at a first input terminal the first clock signal output from the gate circuit, and at a second input terminal the second signal representing the second latency, said logic circuit having an output terminal connected to the second transfer gate.

5. A device according to claim 2, wherein the first clock signal is supplied to a circuit constituting the first stage, and the second clock signal to a circuit constituting the second stage.

6. A device according to claim 2, wherein each of the first and second buffer circuits comprises: a differential amplifier having a first input terminal for receiving a reference voltage and a second input terminal for receiving the clock signal; a flip-flop circuit having first and second input terminals and an output terminal, said first input terminal connected to an output terminal of the differential amplifier; and a delay circuit connected between the output terminal and second input terminal of the flip-flop circuit and having a delay time equal to a difference between a cycle time of the first latency and a cycle of the second latency smaller than the first latency.

7. A semiconductor memory device having a data path divided into first, second and third stages, each having a pipeline structure and designed to operate in synchronism with a clock signal, said device comprising: a signal generating circuit for generating, in response to a command, a first signal representing a first latency and a second signal representing a second latency smaller than the first latency; a buffer circuit for receiving a clock signal; a flip-flop circuit connected to an output terminal of the buffer circuit, for holding a leading edge of the clock signal; a first delay circuit connected between first output terminal and second input terminal of the flip-flop circuit, having a delay time equal to a difference between a cycle time of the first latency and a cycle of the second latency smaller than the first latency, and designed to invert, in accordance with the delay time, a signal output from a second output terminal of the flip-flop circuit; a second delay circuit connected to the second output terminal of the flip-flop circuit, for delaying the signal output from the second output terminal of the flip-flop circuit, by a time nearly equal to a pulse width of the clock signal; a first transfer gate having an input terminal connected to the second output terminal of the flip-flop circuit, to be controlled by the second signal representing the second latency; a second transfer gate having an input terminal connected to an input terminal of the second delay circuit, to be controlled by the second signal representing the second latency; and a gate circuit having a first input terminal connected to an output terminal of the first transfer gate and a second input terminal connected to an output terminal of the second transfer gate, and designed to generate an internal clock signal delayed with respect to the clock signal and used to drive the second stage, in response to the second signal representing the second latency and in response to a signal output from the second output terminal of flip-flop circuit and supplied through the first transfer gate and a signal output from the second delay circuit and supplied through the second transfer gate.

8. A semiconductor memory device comprising: a pipeline structure having a path extending from an address input terminal to a data output terminal, divided into first, second and third stages in accordance with a clock cycle, each designed to operate in synchronism with a clock signal; a command decoder for receiving a plurality of signals and decoding the plurality of signals, thereby to generate a command; a signal generating circuit for generating a first signal representing a first latency and a second signal representing a second latency smaller than the first latency, in response to the command generated by the command decoder; a buffer circuit for receiving a clock signal; a first transfer gate connected to an output terminal of the buffer circuit, for outputting the clock signal output from the buffer circuit as an internal clock signal when turned on by the first signal representing the first latency; a delay circuit connected to the buffer circuit, having a delay time equal to a difference between a cycle time of the first latency and a cycle of the second latency smaller than the first latency, and designed to delay the clock signal output from the buffer circuit; and a second transfer gate connected to an output terminal of the delay circuit, for outputting the clock signal delayed by the delay circuit, as the internal clock signal, when turned on by the second signal representing the second latency.