After a source-drain region is formed, fluorine 24 is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800.degree. C. Through this heat treatment, the dangling binds and the Si--H bonds in the channel regions 26 are substituted by the Si--F bonds, which prevents the generation of the negative bias temperature instability effect in a MOSFET.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a semiconductor device which comprises: forming a gate electrode over a gate insulating film on a silicon substrate; introducing dopants of a predetermined conductive-type into said gate electrode and a surface of said silicon substrate; after said introducing dopants, carrying out a first heat treatment so as to make said dopants within said substrate diffuse and form a source-drain region; and after forming said source-drain region, doping fluorine, at least into said gate electrode and thereafter carrying out a second heat treatment so as to make fluorine diffuse into a channel region of said silicon substrate.
2. The method of manufacturing a semiconductor device according to claim 1, wherein said dopants comprise boron.
3. The method of manufacturing a semiconductor device according to claim 1, wherein said dopants comprise arsenic, phosphorus or antimony.
4. The method of manufacturing a semiconductor device according to claim 1, wherein said doping of fluorine into said gate electrode is carried out by ion implantation at a dose of 1.times.10.sup.13 cm.sup.-2 to 1.times.10.sup.16 cm.sup.-2.
5. The method of manufacturing a semiconductor device according to claim 1, wherein said second heat treatment is carried out at a treatment temperature of 500 to 900.degree. C.
6. A method of manufacturing a semiconductor device which comprises: forming a gate electrode over a gate insulating film on a silicon substrate; introducing dopants of a given conductive-type into said gate electrode and a surface of said silicon substrate; carrying out a first heat treatment so as to make said dopants within said silicon substrate diffuse and form a source-drain region; after forming said source-drain region, forming a silicon nitride film over an entire surface of said semiconductor device; after forming said silicon nitride film, doping fluorine, at least, into said gate electrode and thereafter carrying out a second heat treatment so as to make said fluorine diffuse into a channel region of said silicon substrate.
7. The method of manufacturing a semiconductor device according to claim 6, wherein said dopants comprise boron.
8. The method of manufacturing a semiconductor device according to claim 6, wherein said dopants comprise arsenic, phosphorus or antimony.
9. The method of manufacturing of a semiconductor device according to claim 6, wherein said doping of fluorine into said gate electrode is carried out by ion implantation at a dose of 1.times.10.sup.13 cm.sup.-2 to 1.times.10.sup.16 cm.sup.-2.
10. The method of manufacturing a semiconductor device according to claim 6, wherein said second heat treatment was carried out at a treatment temperature of 500 to 900.degree. C.
11. The method of manufacturing a semiconductor device according to claim 1, wherein a threshold voltage and drain saturation current are substantially constant over time.
12. The method of manufacturing a semiconductor device according to claim 6, wherein a threshold voltage and drain saturation current are substantially constant over time.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 15, 2000
July 17, 2001
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