Chip interconnection structure using stub terminals

1. A method for fabricating a connector for integrated circuit chips comprising the steps of: patterning, masking and etching a silicon substrate to form at least one truncated protrusion having a non-piercing planar upper surface on the at least one truncated protrusion; selectively applying an electrically conductive metal coating on the at least one surface of the substrate and the at least one truncated protrusion; applying at least one insulating layer on the at least one substrate surface; and aligning and joining the substrate having the at least one truncated protrusion to at least one integrated circuit chip having at least one electrically conductive metal pad wherein the at least one metal coated truncated protrusion on said substrate mates with, without piercing, the at least one conductive metal pad of the at least one integrated circuit chip and wherein the electrically conductive metal coatings thereon come into noninvasive contact.

2. A method according to claim 1 wherein the at least one electrically conductive metal pad is disposed in a recess in the integrated circuit chip.

3. A method according to claim 1 wherein the at least one electrically conductive metal pad is disposed co-planar with a surface of the integrated circuit chip.

4. A method according to claim 1 wherein the at least one electrically conductive metal pad is disposed above a surface of the integrated circuit chip.

5. A method according to claim 1 wherein the substrate is etched to form at least first and second truncated protrusions separated by an active device region, and wherein the method includes the step of fabricating an integrated circuit on the active device region of the substrate.

6. A method according to claim 5 wherein the integrated circuit of the active device region of the substrate contains standardized logic circuits and the at least one integrated circuit chip contains customized logic circuits.

7. A method for fabricating a non-invasive connector for integrated circuit chips comprising the steps of: patterning, masking and etching a silicon substrate wherein the silicon substrate is patterned, masked and etched to form a plurality of non-invasive truncated protrusions on the top and bottom surfaces of the silicon substrate, wherein metal is deposited on the plurality of truncated protrusions and wherein a first integrated circuit chip having a plurality of metal pads is aligned and joined to the top surface of the silicon substrate and a second integrated circuit chip having a plurality of metal pads is aligned and joined to the bottom surface of the silicon substrate, wherein the metal-coated truncated protrusions on the top surface of the silicon substrate mate with, without piercing, the metal pads of-the first integrated circuit chip and the metal-coated truncated protrusions on the bottom surface of the silicon substrate mate with, without piercing, the metal pads of the second integrated circuit chip, the method further including the steps of forming at least one silicon via through the silicon substrate and coating the at least one silicon via to provide electrical conduction between the top and bottom sides of the silicon substrate to electrically connect the first and second integrated circuits, and the step of arranging the truncated protrusions and metal pads to key the silicon substrate to the first and second integrated circuit chips.