A non-overlap circuit is provided for a controller of a switching power supply. The controller includes a clock input coupled to a clocking signal, an enable input, a first drive output, and a second drive output. A current source senses the drive outputs, and in response, provides a current source output that switches on and off. A timing capacitor, coupled to the current source, charges when the current source is on. A switch discharges the timing capacitor when the current source is off. A voltage comparator compares the charge level on the timing capacitor to a reference voltage, and outputs a trigger signal to the enable input of the controller when the charge level on the timing capacitor exceeds the reference voltage. When one drive output switches logic state in response to the clocking signal, the current source charges the timing capacitor until the trigger signal causes the other drive output to switch logic state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A non-overlap circuit for a controller of a switching power supply, the controller including a clock input coupled to a clocking signal, an enable input, a first drive output, and a second drive output, the non-overlap circuit comprising: a current source that senses the drive outputs, and in response, provides a current source output that switches on and off; a timing capacitor, coupled to the current source, that charges when the current source is on; a switch that discharges the timing capacitor when the current source is off; and a voltage comparator that compares the charge level on the timing capacitor to a reference voltage, and that outputs a trigger signal to the enable input of the controller when the charge level on the timing capacitor exceeds the reference voltage; wherein when one drive output switches logic state in response to the clocking signal, the current source charges the timing capacitor until the trigger signal causes the other drive output to switch logic state.
2. A non-overlap circuit according to claim 1, wherein the controller includes a flip-flop having the clock input and the enable input, a non-inverting Q output coupled to the first drive output, and an inverting Q-not output coupled to the second drive output.
3. A non-overlap circuit according to claim 2, wherein the controller includes two inverter drivers, one coupled to each flip-flop output, the inverter drivers providing the drive outputs.
4. A non-overlap circuit according to claim 2, wherein the flip-flop includes at least one data sensing input that senses the logic states of the drive outputs, and that determines which drive output is delayed to switch logic states in response to the trigger signal.
5. A non-overlap circuit according to claim 2, wherein the flip-flop includes at least one control signal input that switches between logic states, the control signal being clocked into the flip-flop by the clocking signal.
6. A non-overlap circuit according to claim 1, wherein the switch is a switching transistor.
7. A non-overlap circuit according to claim 1, wherein the current source is temperature independent.
8. A non-overlap circuit according to claim 7, wherein the current source combines the output of a proportional to absolute temperature (PTAT) current source and the output of a complementary to absolute temperature (CTAT) current source.
9. A non-overlap circuit according to claim 1, further comprising: a current source magnitude controller that determines the amount of current supplied by the current source.
10. A non-overlap circuit according to claim 9, wherein the current source magnitude controller is an EPROM encoder.
11. A non-overlap circuit according to claim 1, further comprising: a logic gate that senses the drive outputs, and in response, provides to the current source a logic gate output that switches between logic states.
12. A switching power supply comprising: first and second power switches that, in response to switch drive signals, switch on and off to generate at least one regulated output voltage; and a power switch control module including: a controller having a clock input coupled to a clocking signal, an enable input, and first and second drive outputs providing the switch drive signals; a current source that senses the drive outputs, and in response, provides a current source output that switches on and off; a timing capacitor, coupled to the current source, that charges when the current source is on; a switch that discharges the timing capacitor when the current source is off; and a voltage comparator that compares the charge level on the timing capacitor to a reference voltage, and that outputs a trigger signal to the enable input of the controller when the charge level on the timing capacitor exceeds the reference voltage; wherein when one drive output switches logic state in response to the clocking signal, turning off its associated power switch, the current source charges the timing capacitor until the trigger signal causes the other drive output to switch logic state, turning on its associated power switch.
13. A switching power supply according to claim 12, wherein the controller includes a flip-flop having the clock input and the enable input, a non-inverting Q output coupled to the first drive output, and an inverting Q-not output coupled to the second drive output.
14. A switching power supply according to claim 13, wherein the flip-flop includes at least one data sensing input that senses the logic states of the drive outputs, and that determines which drive output is delayed to switch logic states in response to the trigger signal.
15. A switching power supply according to claim 13, wherein the flip-flop includes at least one control signal input that switches between logic states, the control signal being clocked into the flip-flop by the clocking signal.
16. A switching power supply according to claim 12, wherein the switch is a switching transistor.
17. A switching power supply according to claim 12, further comprising: a current source magnitude controller that determines the amount of current supplied by the current source.
18. A switching power supply according to claim 17, wherein the current source magnitude controller is an EPROM encoder.
19. A switching power supply according to claim 12, further comprising: a logic gate that sense the drive outputs, and in response, provides to the current source a logic gate output that switches between logic states.
20. A method of controlling switch drive signals in a switching power supply having first and second power switches that, in response to the switch drive signals, switch on and off to generate at least one regulated output voltage, the method comprising: providing a controller having a clock input coupled to a clocking signal, an enable input, and first and second drive outputs that provide the switch drive signals; in response to the clocking signal, switching the logic state of the drive output of a power switch that is on, to turn off the power switch that is on; charging a timing capacitor; comparing the charge level on the timing capacitor to a reference voltage, and outputting a trigger signal to the enable input of the controller when the charge level on the timing capacitor exceeds the reference voltage; in response to the trigger signal, switching the logic state of the other drive output to turn on its associated power switch; and discharging the timing capacitor.
21. A method according to claim 20, wherein charging the timing capacitor includes switching on a current source that provides current to the charging capacitor, and discharging the timing capacitor includes switching off the current source.
22. A method according to claim 21, further comprising: setting, with a current source magnitude controller, the amount of current supplied by the current source.
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November 14, 2000
August 14, 2001
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