A method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device by which a gettering ability can be given to an epitaxial wafer in which the formation of BMD is not able to be expected in both low- and high-temperature device manufacturing processes, with the manufacturing processes being lower and higher than 1,050.degree. C. in temperature, and has a specific resistance of .gtoreq.10 m.OMEGA..multidot.cm. When this method is used, such BMD that is sufficient to obtain gettering can be formed in both the low- and high-temperature processes, with the manufacturing processes being lower and higher than 1,050.degree. C. in temperature, even in the epitaxial wafer having a specific resistance of .gtoreq.10 m.OMEGA..multidot.cm by performing low-temperature heat treatment at 650.about.900.degree. C. before starting epitaxial film formation, by selecting the heat-treating time in accordance with the process temperature in the device manufacturing processes and heavy-metal contaminants which are mixed in during the device manufacturing processes can be gettered sufficiently. Therefore, the characteristic deterioration of a device can be prevented and the yield of the device can be improved.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor silicon epitaxial wafer manufacturing method, comprising applying a heat treatment at a temperature of between 650.degree. C. and 900.degree. C. in either an oxygen or nitrogen atmosphere or a mixed gas atmosphere thereof, to a 10 m.OMEGA..multidot.cm or higher substrate resistivity wherein the oxygen concentration is 10.about.less than 14.4.times.10.sup.17 atoms/cm.sup.3 (old ASTM); and p-type (B-doped) CZ-Si wafer, BMD nuclei capable of generating BMD of 5.times.10.sup.4 defects/cm.sup.2.about.5.times.10.sup.5 defects/cm.sup.2 are formed in a 1050.degree. C. or lower temperature device manufacturing process, after which, the wafer is mirror polished on either one side or two sides, and an epitaxial layer is grown on a surface using a vapor-phase growth method.
2. A semiconductor silicon epitaxial wafer manufacturing method, comprising applying a heat treatment at a temperature of between 700.degree. C. and 900.degree. C. in either an oxygen or nitrogen atmosphere or a mixed gas atmosphere thereof, to a 10 m.OMEGA..multidot.cm or higher substrate resistivity wherein the oxygen concentration is 10.about.less than 14.4.times.10.sup.17 atoms/cm.sup.3 (old ASTM); and p-type (B-doped) CZ-Si wafer, BMD nuclei capable of generating BMD of 5.times.10.sup.4 defects/cm.sup.2.about.5.times.10.sup.5 defects/cm.sup.2 are formed in a 1050.degree. C. or higher temperature device manufacturing process, after which, the wafer is mirror polished on either one side or two sides, and an epitaxial layer is grown on a surface using a vapor-phase growth method.
3. A semiconductor silicon epitaxial wafer manufacturing method, comprising applying a heat treatment at a temperature of between 650.degree. C. and 900.degree. C. to a silicon single crystal ingot pulled and removed via the CZ method by controlling the concentration of B so as to obtain a 10 m.OMEGA..multidot.or higher resistivity, p-type (B-doped) CZ-Si wafer, and without performing a process that would produce an EG effect after the ingot has been sliced into silicon wafers, BMD nuclei capable of forming BMD sufficient for gettering are formed in a 1050.degree. C. or lower temperature device manufacturing process, the wafer is mirror polished on either one side or two sides, and an epitaxial layer is grown on a surface using a vapor-phase growth method.
4. The semiconductor silicon epitaxial wafer manufacturing method of claim 3 wherein the BMD density generated by the device manufacturing process is 5.times.10.sup.4 defects/cm.sup.2.about.5.times.10.sup.5 defects/cm.sup.2.
5. The semiconductor silicon epitaxial wafer manufacturing method according to claim 3, wherein the oxygen concentration of the ingot is 10.about.15.times.10.sup.17 atoms/cm.sup.3 (old ASTM).
6. A semiconductor silicon epitaxial wafer manufacturing method, comprising applying a heat treatment at a temperature of between 700.degree. C. and 900.degree. C. to a silicon single crystal ingot pulled and removed via the CZ method by controlling the concentration of B so as to obtain 10 m.OMEGA..multidot.cm or higher resistivity, p-type (B-doped) CZ-Si wafer, and without performing a process that would produce an EG effect after slicing the ingot into silicon wafers, BMD nuclei capable of forming BMD sufficient for gettering are formed in a 1050.degree. C. or higher temperature device manufacturing process, the wafer is mirror polished on either one side or two sides, and an epitaxial layer is grown on a surface using a vapor-phase growth method.
7. The semiconductor silicon epitaxial wafer manufacturing method of claim 6 wherein the BMD density generated by the device manufacturing process is 5.times.10.sup.4 defects/cm.sup.2.about.5.times.10.sup.5 defects/cm.sup.2.
8. semiconductor silicon epitaxial wafer manufacturing method according to claim 6, wherein the concentration of the ingot is 10.about.15.times.10.sup.17 atoms/cm.sup.3 (old ASTM).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 2, 1999
August 21, 2001
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.