A package structure for a semiconductor chip, comprising: a resin substrate having pads formed thereon, a semiconductor chip having electrodes connected to the pads through bumps, an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate, and a stiffener or an elastomer buried in the resin substrate in a portion underneath the semiconductor chip to mitigate or absorb a thermal stress acting between the semiconductor chip, the underfiller and the resin substrate, thereby preventing upward depression of the lower surface of the substrate in a portion underneath the semiconductor chip or preventing fracture of the semiconductor chip.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package structure comprising: a resin substrate having pads formed thereon; a semiconductor chip having electrodes connected to the pads through bumps; an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate; and a stiffener buried in the resin substrate in a portion underneath the semiconductor chip, the stiffener being positioned in a location and having a shape and size sufficient to mitigate a thermal stress acting between the semiconductor chip, the underfiller and the resin substrate, and wherein both an upper surface and a lower surface of the stiffener are exposed relative to the resin substrate.
2. A package structure according to claim 1, wherein the stiffener has a thermal expansion coefficient smaller than that of the resin substrate.
3. A package structure according to claim 1, wherein the stiffener is composed of separate segments buried in the resin substrate in portions underneath corners of the semiconductor chip.
4. A package structure according to claim 1, wherein the stiffener forms a single frame buried in the resin substrate in a portion underneath a periphery of the semiconductor chip.
5. A package structure according to claim 1, wherein the stiffener forms a broad plate buried in the resin substrate in a portion underneath the entire of the semiconductor chip.
6. A package structure according to claim 1, wherein the stiffener is electroconductive and forms a ground electrically connected to a ground line formed on the resin substrate.
7. A package structure according to claim 1, wherein the stiffener has arc-shaped or linearly chamfered corners.
8. A semiconductor package structure comprising: a resin substrate having pads formed thereon; a semiconductor chip having electrodes connected to the pads through bumps; an underfiller filling a space between the semiconductor chip and the resin substrate and bonding the semiconductor chip to the resin substrate; and an elastomer buried in the resin substrate in a portion underneath the semiconductor chip, the elastomer being positioned in a location and having a shape and size sufficient to absorb a thermal stress acting between the semiconductor chip, the underfiller and the resin substrate, wherein both an upper surface and a lower surface of the elastomer are exposed relative to the resin substrate.
9. A package structure according to claim 8, wherein the elastomer is composed of separate segments buried in the resin substrate in portions underneath corners of the semiconductor chip.
10. A package structure according to claim 8, wherein the elastomer forms a single frame buried in the resin substrate in a portion underneath a periphery of the semiconductor chip.
11. A package structure according to claim 8, wherein the elastomer forms a broad plate buried in the resin substrate in a portion underneath the entire semiconductor chip.
12. A package structure according to claim 8, wherein the elastomer has arc-shaped or linearly chamfered corners.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 4, 1999
August 28, 2001
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