An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse duration by the internal timer is disabled by gating the timer output signal with the external signal in a manner such that the gate output signal (which triggers the end of the high voltage pulse) is only generated when the external timing signal has a predetermined value. By controlling the value of the external timing signal, the pulse duration can be varied and have values other than those which would result from use of the internal timer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device comprising: a voltage pulse generator circuit having an output to provide a voltage pulse, wherein a duration time of the voltage pulse is selectively controlled by either an internal timing signal of the memory device or an external timing signal; and a high voltage switch circuit coupled to the voltage pulse generator to receive the voltage pulse, wherein the high voltage switch couples a high voltage signal to internal circuitry for use in memory operations in response to an active state of the voltage pulse.
2. The memory device of claim 1, wherein the voltage pulse generator circuit comprises: a flip-flop to output a selection signal; a logic gate receptive of the selection signal to provide an enable signal; a timer receptive of the enable signal to selectively provide an internal timing signal; and a one shot circuit to reset the flip-flop when the internal timing signal and the external timing signal are at a predetermined logic level.
3. The memory device of claim 2, wherein the flip-flop is receptive to a set signal that has been provided by a state machine.
4. The memory device of claim 1, further comprising: an RS flip-flop to output a selection signal; a NOR gate receptive to the selection signal to provide an enable signal; a timer receptive to the enable signal to provide a timing signal, wherein the timing signal is low when the enable signal is low, wherein the timing signal is high for a predetermined period when the enable signal is high, and wherein the timing signal is low when the predetermined period is over; an OR gate receptive to the timing signal to provide a status signal; and a one-shot receptive to the status signal to provide a reset signal when the status signal is transitioned.
5. The memory device of claim 1, wherein the memory operations are programming or erasing operations.
6. The memory device of claim 1, wherein the memory device is a flash memory device with an array of non-volatile memory cells.
7. A device to produce at least one voltage pulse in a memory system, the device comprising: a state machine to produce a cycle signal; a pulse generator receptive to the cycle signal to produce the at least one voltage pulse; and a duration generator to control a duration of the at least one voltage pulse, wherein the duration generator allows the duration of the at least one voltage pulse to be selectively controlled by at least one of an internal timing signal and an external timing signal.
8. The device of claim 7, wherein the at least one voltage pulse is used for a memory operation that is selected from a group consisting of programming and erasing.
9. The device of claim 7, wherein the memory system includes a non-volatile memory system, wherein the non-volatile memory system includes a flash memory system.
10. The device of claim 7, wherein the state machine initiates a production of the at least one voltage pulse by the pulse generator, wherein the at least one voltage pulse is a high voltage pulse.
11. The device of claim 7, further comprising a one shot, wherein the one shot is activated by the state machine to provide the cycle signal, wherein the cycle signal is a high voltage cycle signal.
12. A device to produce at least one voltage pulse in a memory system, the device comprising: a pulse generator to produce the at least one voltage pulse; and a duration generator to control a duration of the at least one voltage pulse, wherein the duration generator allows the duration of the at least one voltage pulse to be selectively controlled by at least one of an internal timing signal and an external timing signal.
13. The device of claim 12, wherein the pulse generator is receptive to a set signal and a reset signal.
14. The device of claim 13, wherein when the set signal is present and the reset is absent, the pulse generator produces the voltage pulse, wherein the at least one voltage pulse is a high voltage pulse.
15. The device of claim 12, wherein the pulse generator includes a flip-flop, wherein the flip-flop includes a SR flip-flop.
16. The device of claim 12, wherein the at least one voltage pulse is applied to a component in the memory system to connect an external voltage level used in a memory operation, wherein the memory operation is selected from a group consisting of programming and erasing.
17. A device in a memory system, the device comprising: a pulse generator to produce a high voltage pulse, wherein the pulse generator also produces an inverse signal; and a duration generator to control a duration of the voltage pulse, wherein the duration generator is receptive to the inverse signal, wherein the duration generator allows the duration of the voltage pulse to be selectively controlled by at least one of an internal timing signal and an external timing signal.
18. The device of claim 17, wherein the duration generator includes an enable generator, wherein the enable generator is receptive to the inverse signal and the external timing signal to produce an enable signal.
19. The device of claim 18, wherein when the enable signal is at a first predetermined level, the duration of the voltage pulse to be selectively controlled by at least one of an internal timing signal.
20. The device of claim 19, wherein the first predetermine level includes a logic high level.
21. The device of claim 18, wherein the enable generator is a NOR gate.
22. A device in a memory system, the device comprising: a pulse generator to produce a high voltage pulse, wherein the pulse generator also produces an inverse signal; and a duration generator to control a duration of the voltage pulse, wherein the duration generator allows the duration of the voltage pulse to be selectively controlled by at least one of an internal timing signal and an external timing signal, wherein the duration generator includes: an enable generator that is receptive to the inverse signal and the external timing signal to produce an enable signal, wherein the enable signal is at a logic high level when at least one of the inverse signal and the external timing signal is at a logic low level.
23. The device of claim 22, further comprising an internal timer that is receptive to the enable signal to produce the internal timing signal.
24. The device of claim 23, wherein the internal timing signal is at a logic high low level when the enable signal is at a logic low level.
25. The device of claim 23, wherein the internal timing signal is at a logic high level when the enable signal is at a logic level, wherein a logic high level until a predetermined period is over, wherein when the predetermined period is over, the enable signal transitions from a logic high level to a logic low level.
26. The device of claim 25, wherein the predetermined period is over when the internal timer times out.
27. The device of claim 26, wherein the predetermined period defines the duration of the voltage pulse that is controlled by the internal timing signal.
28. A device in a memory system, the device comprising: a pulse generator to produce a high voltage pulse, wherein the pulse generater also produces an inverse signal; and a duration generator to control a duration of the voltage pulse, wherein the duration generator allows the duration of the voltage pulse, to be selectively controlled by at least one of an internal timing signal, wherein the duration generator includes: an enable generator that is receptive to the inverse signal and the external timing signal to produce an enable signal, wherein the enable signal is at a logic high when both of the inverse signal and the external timing signal is at a logic low level;and an internal timer that is receptive to the enable signal to produce the internal timing signal, wherein the internal timing signal is at a logic high level when the enable signal is at a logic high level, wherein the internal timing signal remains at a logic high level until a predetermined period is over, wherein when the predetermined period is over, the internal timing signal transitions from a logic high level to a logic low level.
29. The device of claim 28, wherein the voltage pulse is produced during the predetermined period, and wherein the inverse signal is at a logic low level.
30. The device of claim 28, wherein when the predetermined period is over, the pulse generator terminates producing the high voltage pulse.
31. A device in a memory system, the device comprising: a pulse generator to produce a high voltage pulse, wherein the pulse generator also produces an inverse signal; and a duration generator to control a duration of the voltage pulse, wherein the duration generator allows the duration of the voltage pulse to be selectively controlled by at least one of an internal timing signal and an external timing signal, wherein the duration generator includes: an enable generator that is receptive to the inverse signal and the external timing signal to produce an enable signal, wherein the enable signal is at a logic low level when at least one of the inverse signal and the external timing signal is at a logic high level; and an internal timer that is receptive to the enable signal to produce the internal timing signal, wherein the internal timer produces the internal timing signal at a logic low level when the enable signal is at a logic low level.
32. The device of claim 31, further comprising a control generator that is receptive to the internal timing signal and the external timing signal to produce a control pulse.
33. The device of claim 32, wherein when the control generator receives initially the external timing signal at a logic high level and receives subsequently the external timing signal at a logic low level after a predetermined period of time, the control generator generates the control pulse.
34. The device of claim 33, wherein the pulse generator produces the high voltage pulse during the predetermined period of time.
35. The device of claim 33, wherein the pulse generator terminates producing the high voltage pulse when the pulse generator receives the control pulse.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 4, 1999
August 28, 2001
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.