A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several one-shot internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An output enable circuit for an integrated circuit device, said circuit comprising: a clock buffer for receiving an external clock signal and producing an internal clock signal displaced from said external clock signal by a delay imposed by said clock buffer circuit; a reset circuit coupled to said clock buffer circuit for producing a reset clock signal displaced from said internal clock signal by a delay imposed by said reset circuit; at least one output enable logic circuit coupled to receive said internal clock signal and said reset clock signal, said output enable logic circuit producing an output enable clock signal having a first state thereof initiated on a first logic level transition of said internal clock signal and a second state thereof initiated on an opposite second logic level transition of said reset clock signal; and at least one pass gate coupled to receive said output enable clock signal and a data signal, said pass gate operative to provide said data signal to an output node when said output enable clock signal is in said first state thereof.
2. The circuit of claim 1 further comprising a logic gate interposed between said reset circuit and said output enable logic circuit, said logic gate having an enable input thereof for providing said reset clock signal to said output enable logic circuit when said enable input is asserted.
3. The circuit of claim 2 wherein said logic gate comprises a NAND gate.
4. The circuit of claim 3 wherein said logic gate further comprises an inverting amplifier coupled in series with said NAND gate.
5. The circuit of claim 1 wherein said clock buffer comprises at least one amplifier stage.
6. The circuit of claim 5 wherein said clock buffer comprises no more than two amplifier stages.
7. The circuit of claim 1 wherein said reset circuit comprises an odd number of series coupled inverting amplifier stages.
8. The circuit of claim 7 wherein said reset circuit comprises no more than three inverting amplifier stages.
9. The circuit of claim 1 further comprising an output buffer coupling said output node to an output pad.
10. The circuit of claim 9 wherein said output buffer comprises at least one amplification stage.
11. The circuit of claim 10 wherein said output buffer comprises no more than two amplification stages.
12. The circuit of claim 1 wherein said at least one output enable logic circuit and said at least one pass gate comprise a plurality of said output enable logic circuits and associated pass gates receiving a like plurality of data signals.
13. The circuit of claim 12 wherein said plurality of associated pass gates are alternatively enablable by said plurality of said output enable logic circuits to alternatively provide said plurality of data signals to said output node.
14. The circuit of claim 1 wherein said at least one output enable circuit comprises a two-input NAND gate.
15. The circuit of claim 14 wherein said NAND gate comprises first, second, third and fourth transistors, said first, second and third transistors being coupled in series between a supply voltage source and circuit ground and said fourth transistor being coupled between said supply voltage source and an output enable node intermediate said first and second transistors, said first and second transistors having common connected control terminals thereof coupled to receive said internal clock signal and said third and fourth transistors having common connected control terminals thereof coupled to receive said reset clock signal, said output enable clock signal being provided at said output enable node.
16. The circuit of claim 15 wherein said first and fourth transistors are p-channel devices and said second and third transistors are n-channel devices.
17. The circuit of claim 15 wherein said first transistor is relatively small and said third and fourth transistors are relatively large compared to said second transistor.
18. The circuit of claim 1 wherein said internal clock signal and said reset clock signal have a given delay and said output enable clock signal has a duty cycle independent of said external clock signal.
19. The circuit of claim 1 wherein said integrated circuit device comprises a memory device.
20. The circuit of claim 19 wherein said memory device comprises a synchronous dynamic random access memory device.
21. A process for multiplexing data from multiple data sources to a common output node on an integrated circuit device, said process comprising: supplying an external clock signal to said integrated circuit device; buffering said external clock signal to provide an internal clock signal having n gate delays; delaying said internal clock signal to provide a reset clock signal having an odd number of additional gate delays; producing at least one output enable clock signal having a first state thereof initiated on a first logic level transition of said internal clock signal and a second state thereof initiated on an opposite second logic level transition of said reset clock signal; and passing data corresponding to one of said data sources to said common output node in response to said output enable clock signal being in said first state thereof.
22. The process of claim 21 wherein said step of buffering said external clock signal is carried out by means of a clock buffer having no more than two series coupled amplification stages.
23. The process of claim 21 wherein said step of delaying said internal clock signal is carried out by means of a reset circuit having an odd number of series coupled inverting amplification stages.
24. The process of claim 21 wherein said step of producing at least one output enable clock signal comprises the steps of: alternatively producing plural output enable clock signals; and alternatively passing data from a plural number of said multiple data sources to said common output node in response to each of said plural output enable clock signals being respectively in said first state thereof.
25. The process of claim 21 wherein said step of producing is carried out by means of an output enable logic circuit.
26. The process of claim 21 wherein said step of passing is carried out by means of a pass transistor coupled to said common output node and coupled to receive said data from one of said multiple data sources and said output enable clock signal at a control terminal thereof.
27. The process of claim 21 further comprising the steps of: amplifying a data signal on said common output node; and providing said amplified data signal to an external output pad of said integrated circuit device.
28. The process of claim 27 wherein said step of amplifying is carried out by an output buffer having no more than two series coupled amplification stages.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 17, 1998
September 4, 2001
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