A multi-monitor computer system (10) includes a configuration address space (40) for software driven initialization and configuration. A monitor synchronization method (50) of this invention includes temporarily remapping multiple graphics chips (14, 18) to a same base address (46) so that attempts to write to a memory mapped register on one of the graphics chips, also writes the same register on the other graphics chips. Once the addresses are remapped, writing chip enabling data to an enabling register on one of the graphics chips causes enabling data to be written to all graphics chips at the same time, thereby synchronizing the vertical and horizontal sync signals generated by the graphics chips. Finally, remapping the graphics chips to their original base memory addresses allows the computer system to resume selective addressing of the graphics chips, which now provide synchronized vertical and horizontal sync signals to their respective monitors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of synchronizing vertical and horizontal sync signals driving multiple displays driven from a single computer system: comprising: interfacing multiple graphics chips to the single computer system; temporarily remapping the multiple graphics chips to a same base memory address in the single computer system so that writing data to a memory mapped register on at least one of the multiple graphics chips causes the data to be written to the same memory mapped register on all of the graphics chips; writing enabling data to a chip enabling register on at least one of the multiple graphics chips, thereby synchronously starting the vertical and horizontal sync signals on all of the graphics chips; and synchronously driving multiple monitors from associated ones of the multiple graphics chips.
2. The method of claim 1 further including remapping the multiple graphics chips to different base memory addresses to restore a selective addressing capability to the multiple memory chips.
3. The method if claim 1 in which synchronously driving multiple monitors eliminates a visible effect of electromagnetic coupling between the monitors.
4. The method of claim 1 in which the method is carried out during at least one of an initialization process, a repetitive time period, and a period of selectively addressing an alternate monitor.
5. The method of claim 1 in which the multiple graphics chips include a graphics accelerator functionality.
6. The method of claim 1 in which the multiple graphics chips are VGA compliant.
7. The method of claim 1 in which the computer system is PCI compliant.
8. A method of synchronizing sync signals driving first and second displays driven from a single computer system: comprising: interfacing first and second graphics chips to the single computer system; writing enabling data to a chip enabling register on the first graphics chip, thereby generating a first sync signal on the first graphics chip; waiting a predetermined amount of time; writing enabling data to a chip enabling register on the second graphics chip, thereby generating a second sync signal on the second graphics chip, the first and second sync signals being spaced apart by about the predetermined amount of time; and driving first and second monitors from associated ones of the first and second graphics chips.
9. The method of claim 8 in which the first and second sync signals are vertical sync signals.
10. The method of claim 8 in which the predetermined amount of time ranges from about 1 millisecond to about 33 milliseconds.
11. The method of claim 8 in which the predetermined amount of time is an amount of time that causes interference-causing electromagnetic radiation to occur within a vertical blanking period of an affected monitor.
12. The method of claim 8 in which the first and second graphics chips are VGA compliant.
13. The method of claim 8 in which the computer system is PCI compliant.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 1, 1999
October 2, 2001
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