A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits includes the steps of providing a circuit having CMOS objects, defining a beta ratio; resizing the CMOS objects based on the beta ratio, determining if the objects are a minimum size based on predetermined size criteria, if the objects are larger than the minimum size, defining a scaling factor based on a performance level of the object and resizing the object based on the scaling factor such that delay variations of the resized circuit are substantially constant. Also, a computer program product is provided for reducing the hysteresis effect.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits comprising the steps of: providing a circuit having CMOS objects included therein by providing a bulk silicon CMOS circuit and remapping the bulk silicon CMOS circuit to provide a silicon-on-insulator CMOS circuit; defining a beta ratio based on CMOS object widths so as to reduce the beta ratio while maintaining performance for the CMOS objects above a threshold performance; and resizing the CMOS objects based on the beta ratio such that delay variations of the resized circuit are substantially constant over time.
2. The method as recited in claim 1, wherein the step of defining the beta ratio includes the step of calculating the beta ratio by dividing a pullup width by a pulldown width for the CMOS objects.
3. The method as recited in claim 1, wherein the step of resizing includes the step of reducing gate sizes of the objects thereby reducing capacitive loads and increasing circuit speed.
4. The method as recited in claim 1, wherein the step of defining the beta ratio includes the step of defining a default beta ratio for the circuit having CMOS objects.
5. The method as recited in claim 1, wherein the objects include one of gates, devices and circuits.
6. A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits comprising the steps of: providing a circuit having CMOS objects by providing a bulk silicon CMOS circuit and remapping the bulk silicon CMOS circuit to provide a silicon-on-insulator CMOS circuit; reducing a beta ratio while maintaining performance for the CMOS objects above a threshold performance; resizing the CMOS objects based on the beta ratio; determining if the objects are a minimum size based on predetermined size criteria; if the objects are larger than the minimum size, defining a scaling factor based on a performance level of the object; and resizing the object based on the scaling factor such that delay variations of the resized circuit are substantially constant over time.
7. The method as recited in claim 6, wherein the step of defining the beta ratio includes the step of calculating the beta ratio by dividing a pullup width by a pulldown width for the CMOS objects.
8. The method as recited in claim 6, wherein the step of resizing the CMOS objects based on the beta ratio includes the step of reducing gate sizes of the objects thereby reducing capacitive loads and increasing circuit speed.
9. The method as recited in claim 6, wherein the step of defining the beta ratio includes the step of defining a default beta ratio for the circuit having CMOS objects.
10. The method as recited in claim 6, wherein the objects include one of gates, devices and circuits.
11. The method as recited in claim 6, wherein the step of determining if the objects are a minimum size based on predetermined size criteria include the step of determining if the objects are a minimum size based on the beta ratio.
12. The method as recited in claim 6, wherein the step of defining a scaling factor based on a performance level of the object includes the step of defining a scaling factor based on a current ratio, the current ratio being calculated as the ratio between a first current needed to drive a load, and a second current needed to drive the same load after an object to drive the load is resized.
13. A computer program product comprising: a computer usable medium having computer readable program code embodied therein for sizing silicon-on-insulator CMOS circuits for reducing a hysteresis effect, the computer readable program code in the computer program product comprising: computer readable program code for causing a computer to represent a circuit having CMOS objects, including program code for representing a bulk silicon CMOS circuit and for remapping the bulk silicon CMOS circuit to provide a silicon-on-insulator CMOS circuit; computer readable program code for causing a computer to define a beta ratio so as to reduce the beta ratio while maintaining performance for the CMOS object above a threshold performance; computer readable program code for causing a computer to resize the CMOS objects based on the beta ratio; computer readable program code for causing a computer to determine if the objects are a minimum size based on predetermined size criteria; computer readable program code for causing a computer to define a scaling factor based on a performance level of the object, if the objects are larger than the minimum size; and computer readable program code for causing a computer to resize the object based on the scaling factor such that delay variations of the resized circuit are substantially constant over time.
14. The computer program product as recited in claim 13, wherein the program code for causing the computer to define the beta ratio includes program code for calculating the beta ratio by dividing a pullup width by a pulldown width for the CMOS objects.
15. The computer program product as recited in claim 13, wherein the program code for causing the computer to resize the CMOS objects based on the beta ratio includes program code for reducing gate sizes of the objects thereby reducing capacitive loads and increasing circuit speed.
16. The computer program product as recited in claim 13, wherein the program code for causing the computer to define the beta ratio includes program code for defining a default beta ratio for the circuit having CMOS objects.
17. The computer program product as recited in claim 13, wherein the objects include one of gates, devices and circuits.
18. The computer program product as recited in claim 13, wherein the program code for causing the computer to determine if the objects are a minimum size based on predetermined size criteria includes program code for determining if the objects are a minimum size based on the beta ratio.
19. The computer program product as recited in claim 13, wherein the program code for causing the computer to define a scaling factor based on a performance level of the object includes program code for defining a scaling factor based on a current ratio, the current ratio being calculated as the ratio between a first current needed to drive a load, and a second current needed to drive the same load after an object to drive the load is resized.
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November 10, 1998
October 2, 2001
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