An enhanced bus turnaround integrated circuit dynamic random access memory (DRAM) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (ZBT), or pipeline burst static random access memory (SRAM) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a Wait pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; outputting said read data on said data bus from said at least one static register; performing a refresh operation to said at least one dynamic random access memory array during at least a portion of said step of outputting said read data; and providing a wait signal output from said memory device indicative of said refresh operation.
2. The method of claim 1 further comprising: generating an internal hit signal in response to said other address signals if said at least a portion of said read data is currently stored in said at least one static register; and obviating said step of storing said at least a portion of said read data to said at least one static register.
3. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; automatically initiating a periodic refresh operation to said at least one dynamic random access memory array; asserting a refresh inhibit signal to said memory device; and inhibiting said periodic refresh operation for a predetermined time period in response to said asserted refresh inhibit signal.
4. The method of claim 3 further comprising: outputting said read data on said data bus from said at least one static register during at least a portion of said periodic refresh operation.
5. The method of claim 3 further comprising: initiating at least one refresh operation to said at least one dynamic random access memory array following said predetermined time period.
6. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; automatically initiating a periodic refresh operation to said at least one dynamic random access memory array; asserting a refresh inhibit signal to another associated memory device; and synchronizing said periodic refresh operation of said memory device and said another memory device in response to said refresh inhibit signal.
7. The method of claim 6 further comprising: outputting said read data on said data bus from said at least one static register during at least a portion of said periodic refresh operation.
8. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; automatically initiating a periodic refresh operation to said at least one dynamic random access memory array; asserting a refresh signal to another associated memory device indicative of a commencement of said refresh operation to said at least one dynamic random access memory array; and outputting said read data on said data bus from said at least one static register during at least a portion of said periodic refresh operation.
9. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; automatically initiating a periodic refresh operation to said at least one dynamic random access memory array; asserting a mode signal to said memory device; alternatively commencing said refresh in response to said asserted mode signal; and outputting said read data on said data bus from said at least one static register during at least a portion of said periodic refresh operation.
10. A method for operating an integrated circuit memory device having an address bus and a data bus, said method comprising: providing at least one dynamic random access memory array having at least one static register associated therewith; placing address signals on said address bus corresponding to a selected memory location in said at least one dynamic random access memory array; inputting data signals on said data bus corresponding to write data to be written to said selected memory location in said at least one dynamic random access memory array; placing other address signals on said address bus corresponding to read data to be read from another selected memory location in said at least one dynamic random access memory array; storing at least a portion of said read data to said at least one static register; automatically initiating a precharge operation to at least a portion of said at least one dynamic random access memory array; asserting a chip enable signal to said memory device; and alternatively commencing said precharge operation to any open pages in said at least a portion of said at least one dynamic random access memory array in response to said asserted chip enable signal.
11. The method of claim 10 further comprising: outputting said read data on said data bus from said at least one static register during at least a portion of said precharge operation.
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July 27, 2000
October 9, 2001
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