A method and apparatus for processing memory access requests having enhanced functionality includes processing that begins by receiving a memory access request. The process continues by determining whether the memory access request triggers an address caching process to be performed. If so, the address caching process is performed. While performing the address caching process, a determination is made as to whether the address caching processing triggers an exception process to be performed based upon a physical address derived from the address caching process. Such address space requiring further processing includes video graphics address space, restricted memory space, read-only memory space, non-cacheable data memory space, device emulation exceptions memory space, and memory exceptions. When the exception process is triggered during the address caching process, the exception process is performed and the results are cached in an address processing cache.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for processing memory accesses, the method comprises the steps of: a) receiving a memory access request; b) determining whether the memory access request triggers an address caching process to be performed; c) when the memory access requests triggers the address caching process to be performed, commencing performance of the address caching process; d) determining whether the address caching process triggers an exception process utilizing entries within a TLB to be performed based upon a physical address derived from the memory access request; and e) when the address caching process triggers an exception process to be performed, performing the exception process.
2. The method of claim 1, wherein step (b) further comprises: performing a translation look aside table (TLB) look up; and when a corresponding TLB entry does not exist in the TLB, translating a virtual address identified in the memory access request into the physical address.
3. The method of claim 2, wherein step (c) further comprises: generating the TLB entry to describe the virtual address to a physical address translation; and storing the TLB entry in the TLB.
4. The method of claim 3, wherein step (d) further comprises determining whether the physical address is within an exception address range of at least one exception address ranges.
5. The method of claim 4 further comprises: changing the exception address range; and clearing the TLB when the exception address range is changed.
6. The method of claim 3, wherein the exception process further comprises at least one of: restricting access to reserved memory locations, performing further address translations, changing data caching attributes, emulating hardware devices, switching between address spaces, creating an altered TLB entry that differs from the TLB entry.
7. The method of claim 6 further comprises caching the altered TLB entry.
8. The method of claim 1, wherein step (e) further comprises emulating, as the exception process, the memory access request.
9. A method for processing memory accesses, the method comprises the steps of: a) receiving a memory access request; b) determining whether a translation look aside table (TLB) entry exists for memory locations identified by the memory access; c) when the TLB entry does not exist, commencing generation of the TLB entry; d) determining whether the generating of the TLB entry triggers an exception process to be performed based upon a physical address derived from the memory access request; and e) when the generating of the TLB entry triggers an exception process to be performed, performing the exception process.
10. The method of claim 9, wherein step (c) further comprises: generating the TLB entry to describe the virtual address to a physical address translation; and caching the TLB entry in the TLB.
11. The method of claim 10, wherein step (d) further comprises determining whether the physical address is within an exception address range of at least one exception address ranges.
12. The method of claim 11 further comprises: changing the exception address range; and clearing the TLB when the exception address range is changed.
13. The method of claim 10, wherein the exception process further comprises at least one of: restricting access to reserved memory locations, performing further address translations, changing data caching attributes, emulating hardware devices, switching between address spaces, creating an altered TLB entry that differs from the TLB entry.
14. The method of claim 9, wherein step (e) further comprises emulating, as the exception process, the memory access request.
15. A memory access processing module comprises: a processing device; and memory operably coupled to the processing device, wherein the memory stores operational instructions that cause the processing device to: (a) receive a memory access request; (b) determine whether the memory access request triggers an address caching process to be performed; (c) commence performance of the address caching process when the memory access requests triggers the address caching process to be performed; (d) determine whether the address caching process triggers an exception process utilizing entries within a TLB to be performed based upon a physical address derived from the memory access request; and (e) perform the exception when the address caching process triggers an exception process to be performed.
16. The memory access processing module of claim 15, wherein the memory further comprises operational instructions that cause the processing device to determine whether the memory access request triggers the address caching process by: performing a translation look aside table (TLB) look up; and when a corresponding TLB entry does not exist in the TLB, translating a virtual address identified in the memory access request into the physical address.
17. The memory access processing module of claim 16, wherein the memory further comprises operational instructions that cause the processing device to: generate the TLB entry to describe the virtual address to a physical address translation; and store the TLB entry in the TLB.
18. The memory access processing module of claim 16, wherein the memory further comprises operational instructions that cause the processing device to determine whether the physical address is within an exception address range of at least one exception address ranges.
19. The memory access processing module of claim 18, wherein the memory further comprises operational instructions that cause the processing device to: change the exception address range; and clear the TLB when the exception address range is changed.
20. The memory access processing module of claim 16, wherein the exception process further comprises at least one of: restricting access to reserved memory locations, performing further address translations, changing data caching attributes, emulating hardware devices, switching between address spaces, creating an altered TLB entry that differs from the TLB entry.
21. The memory access processing module of claim 15, wherein the memory further comprises operational instructions that cause the processing device to emulate, as the exception process, the memory access request.
22. A memory access processing module comprises: a processing device; and memory operably coupled to the processing device, wherein the memory stores operational instructions that cause the processing device to: (a) receive a memory access request; (b) determine whether a translation look aside table (TLB) entry exists for memory locations identified by the memory access; (c) commence generation of the TLB entry when the TLB entry does not exist; (d) determine whether the generating of the TLB entry triggers an exception process utilizing entries within a TLB to be performed based upon a physical address derived from the memory access request; and (e) perform the exception process when the generating of the TLB entry triggers an exception process to be performed.
23. The memory access processing module of claim 21, wherein the memory further comprises operational instructions that cause the processing device to: generate the TLB entry to describe the virtual address to a physical address translation; and cache the TLB entry in the TLB.
24. The memory access processing module of claim 22, wherein the memory further comprises operational instructions that cause the processing device to determine whether the physical address is within an exception address range of at least one exception address ranges.
25. The memory access processing module of claim 23, wherein the memory further comprises operational instructions that cause the processing device to: change the exception address range; and clear the TLB when the exception address range is changed.
26. The memory access processing module of claim 21, wherein the exception process further comprises at least one of: restricting access to reserved memory locations, performing further address translations, changing data caching attributes, emulating hardware devices, switching between address spaces, creating an altered TLB entry that differs from the TLB entry.
27. The memory access processing module of claim 21, wherein the memory further comprises operational instructions that cause the processing device to emulate, as the exception process, the memory access request.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 18, 1999
October 9, 2001
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.