Patentable/Patents/US-6303994
US-6303994

Method and apparatus for reducing the first wafer effect

PublishedOctober 16, 2001
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method and apparatus are provided for reducing and eliminating the First Wafer Effect. Specifically, in a method, or system that employs a separate hot chamber for hot deposition of material that may result in the First Wafer Effect (FWE material), a cold layer of the FWE material is deposited within the hot deposition chamber prior to deposition of the hot FWE material layer.

Patent Claims
19 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A solid state electronic device produced by: depositing a first film at a first wafer temperature in a first deposition chamber; depositing a second film at a second wafer temperature in a second deposition chamber; and depositing a third film at a third wafer temperature in the second deposition chamber; wherein the second and third films are consecutively deposited from a common source of an FWE material, the third temperature is higher than the second temperature and the first film comprises the FWE material.

2

2. A solid state electronic device produced by: depositing a first film at a first wafer temperature in a first deposition chamber; depositing a second film at a second wafer temperature in a second deposition chamber; and depositing a third film at a third wafer temperature in the second deposition chamber; wherein the second and third films are consecutively deposited from a common source of an FWE material, the third temperature is higher than the second temperature and the first film comprises the FWE material; and wherein the first, second and third wafer temperatures and a thickness of the second film are such that when an idle period occurs, a third film of a first wafer deposited following the idle period exhibits a first reflectance which is substantially equivalent to a second reflectance exhibited by a third film of a subsequent wafer deposited during normal production.

3

3. A semiconductor device fabrication system comprising: a first deposition chamber for depositing a first film at a first temperature; a second deposition chamber, operatively coupled to the first deposition chamber, for depositing a second film at a second temperature and for depositing a third film at a third temperature; and a controller, operatively coupled to at least the second deposition chamber, for causing the second deposition chamber to consecutively deposit the second film and the third film from a common source of a FWE material; wherein the first, second and third temperatures and a thickness of the second film, are such that when an idle period occurs, a third film of a first wafer deposited following the idle period exhibits a first reflectance which is substantially equal to a second reflectance exhibited by a third film of a subsequent wafer deposited during normal production.

4

4. The system of claim 3 wherein the first deposition chamber comprises a first source of the FWE material.

5

5. The system of claim 4 further comprising a wetting layer chamber operatively coupled to the first deposition chamber for depositing a wetting layer prior to deposition of the first film.

6

6. The system of claim 5 wherein the wetting layer chamber comprises a titanium source.

7

7. The system of claim 5 wherein the first deposition chamber is a long throw deposition chamber.

8

8. The system of claim 7 wherein the second deposition chamber is a standard throw deposition chamber.

9

9. The system of claim 8 wherein the first deposition chamber comprises a particle screening device.

10

10. The system of claim 3 wherein the first film is deposited at a first pressure, the second film is deposited at a second pressure and the third film is deposited at a third pressure.

11

11. The system of claim 10 wherein said first chamber and said second chamber are a single chamber.

12

12. The system of claim 10 wherein the first temperature, the second temperature and the third temperature are a single temperature.

13

13. A solid state electronic device comprising: a first FWE material film comprising a small grain structure; a second FWE material film on said first FWE material film, said second FWE material film having a small grain structure and a first oxygen concentration; a third FWE material film on said second FWE material film, said third FWE material film having a large grain structure and a second oxygen concentration; wherein the first oxygen concentration is higher than the second oxygen concentration.

14

14. The device of claim 13 wherein the third FWE material film comprises a crystal orientation having a narrow distribution.

15

15. The device of claim 14 wherein said first FWE material film comprises a FWE material, said second FWE material film comprises the FWE material and the third FWE material film comprises the FWE material.

16

16. The device of claim 15 wherein the FWE material layer is aluminum.

17

17. The device of claim 15 wherein the FWE material is an aluminum alloy.

18

18. The device of claim 16 further comprising a titanium wetting layer, wherein the first FWE material layer is on said wetting layer.

19

19. The device of claim 17 further comprising a titanium wetting layer, wherein the first FWE material layer is on said wetting layer.

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Patent Metadata

Filing Date

June 13, 2000

Publication Date

October 16, 2001

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