A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated read only memory device comprising: at least one memory cell comprising a semiconductor substrate, a storage transistor in said semiconductor substrate and having a first conduction terminal connected to a reference voltage, a word line connected to a control terminal of said storage transistor, and a plurality of auxiliary bit lines for connection to a second conduction terminal of said storage transistor, at most one of said plurality of auxiliary bit lines being connected to the second conduction terminal of said storage transistor at a time.
2. The integrated read only memory device according to claim 1 wherein said plurality of auxiliary bit lines are situated one above another on respective metallization levels above said semiconductor substrate.
3. The integrated read only memory device according to claim 2 wherein said at least one memory cell further comprises a pillar connecting the second conduction terminal of said storage transistor to each of the metallization levels.
4. The integrated read only memory device according to claim 3 further comprising a horizontal connection connecting at most one of said plurality of auxiliary bit lines to said pillar.
5. The integrated read only memory device according to claim 3 wherein said pillar comprises metal.
6. The integrated read only memory device according to claim 1 wherein said plurality of auxiliary bit lines comprises three auxiliary bit lines; and further comprising a conversion circuit comprising: three inputs respectively connected to said three auxiliary bit lines; two outputs; and a logic circuit connected between the three inputs and the two outputs for converting a value stored in said at least one memory cell into a two bit output word.
7. The integrated read only memory device according to claim 1 wherein said at least one memory cell comprises two memory cells; wherein said plurality of auxiliary bit lines comprises two auxiliary bit lines; and further comprising a ternary/binary conversion circuit comprising: four inputs respectively connected to each of said two auxiliary bit lines of said two memory cells; four outputs; and a conversion logic circuit connected between said four inputs and said four outputs for converting a value stored in said two memory cells into a three bit output word and a check bit.
8. The integrated read only memory device according to claim 7 wherein said conversion logic circuit comprises: a NOR logic gate; and a 3-bit binary adder having three outputs connected to three of said four outputs to provide the three bit output word and a carry output connected to the other of said four outputs to provide the check bit.
9. The integrated read only memory device according to claim 1 wherein said plurality of auxiliary bit lines are alongside one another on a predetermined metallization level.
10. The integrated read only memory device according to claim 9 wherein the at least one memory cell further comprises: a connection line situated at an intermediate metallization level between said semiconductor substrate and the predetermined metallization level; and a pillar having a first end connected to the second conduction terminal of said storage transistor and a second end connected to said connection line.
11. The integrated read only memory device according to claim 10 wherein said pillar comprises metal.
12. The integrated read only memory device according to claim 10 further comprising a vertical connection connecting at most one of said plurality of auxiliary bit lines to said connection line.
13. The integrated read only memory device according to claim 1 wherein said storage transistor comprises a MOS transistor, wherein the first conduction terminal comprises a source of said MOS transistor, wherein the second conduction terminal comprises a drain of said MOS transistor, and wherein the control terminal comprises a gate of said MOS transistor.
14. An integrated read only memory device comprising: at least one memory cell comprising a semiconductor substrate, a storage transistor in said semiconductor substrate and having a first conduction terminal connected to a reference voltage, a word line connected to a control terminal of said storage transistor, a plurality of auxiliary bit lines, situated one above another on respective metallization levels above the semiconductor substrate, for connection to a second conduction terminal of said storage transistor, at most one of said plurality of auxiliary bit lines being connected to the second conduction terminal of said storage transistor at a time, and a pillar connecting the second conduction terminal of said storage transistor to each of the metallization levels.
15. The integrated read only memory device according to claim 14 further comprising a horizontal connection connecting at most one of said plurality of auxiliary bit lines to said pillar.
16. The integrated read only memory device according to claim 14 wherein said pillar comprises metal.
17. The integrated read only memory device according to claim 14 wherein said storage transistor comprises a MOS transistor, wherein the first conduction terminal comprises a source of said MOS transistor, wherein the second conduction terminal comprises a drain of said MOS transistor, and wherein the control terminal comprises a gate of said MOS transistor.
18. An integrated read only memory device comprising: at least one memory cell comprising a semiconductor substrate, a storage transistor in said semiconductor substrate and having a first conduction terminal connected to a reference voltage, a word line connected to a control terminal of said storage transistor, and a plurality of auxiliary bit lines, each alongside one another on a predetermined metallization level, for connection to a second conduction terminal of said storage transistor, at most one of said plurality of auxiliary bit lines being connected to the second conduction terminal of said storage transistor at a time, a connection line situated at an intermediate metallization level between said semiconductor substrate and the predetermined metallization level, and a pillar having a first end connected to the second conduction terminal of said storage transistor and a second end connected to said connection line.
19. The integrated read only memory device according to claim 18 wherein said pillar comprises metal.
20. The integrated read only memory device according to claim 18 further comprising a vertical connection connecting at most one of said plurality of auxiliary bit lines to said connection line.
21. The integrated read only memory device according to claim 18 wherein said storage transistor comprises a MOS transistor, wherein the first conduction terminal comprises a source of said MOS transistor, wherein the second conduction terminal comprises a drain of said MOS transistor, and wherein the control terminal comprises a gate of said MOS transistor.
22. A integrated read only memory device comprising: a memory block comprising a main memory cell comprising a semiconductor substrate, a storage transistor in said semiconductor substrate and having a first conduction terminal connected to a reference voltage, a word line connected to a control terminal of said storage transistor, and at least three auxiliary bit lines for connection to a second conduction terminal of said storage transistor, at most one of the at least three auxiliary bit lines being connected to the second conduction terminal of said storage transistor at a time; and a plurality of ancillary memory cells each comprising an ancillary storage transistor connected to the word line of said main memory cell and an ancillary bit line for connection to a conduction terminal of said ancillary storage transistor.
23. The integrated read only memory device according to claim 22 wherein said at least three auxiliary bit lines are situated alongside one another on a predetermined metallization level above said semiconductor substrate.
24. The integrated read only memory device according to claim 23 wherein said main memory cell further comprises: a connection line situated at an intermediate metallization level between said semiconductor substrate and the predetermined metallization level; and a pillar having a first end connected to the second conduction terminal of said storage transistor and a second end connected to said connection line.
25. The integrated read only memory device of claim 24 wherein said ancillary bit lines are situated on either side of said pillar on a lower metallization level situated under said connection line.
26. The integrated read only memory device of claim 25 wherein each ancillary bit line is situated under one of said at least three auxiliary bit lines of said main memory cell; wherein said plurality of ancillary memory cells comprises two ancillary memory cells; and wherein the integrated read only memory device further comprises a conversion circuit comprising: five inputs respectively connected to said at least three auxiliary bit lines and said two ancillary bit lines, four outputs, and a logic circuit connected between said five inputs and said four outputs for converting a value stored in said memory block into a four bit output word.
27. The integrated read only memory device according to claim 22 wherein said storage transistor comprises a MOS transistor, wherein the first conduction terminal comprises a source of said MOS transistor, wherein the second conduction terminal comprises a drain of said MOS transistor, and wherein the control terminal comprises a gate of said MOS transistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 9, 2000
October 16, 2001
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